公开(公告)号：US20200067513A1

公开(公告)日：2020-02-27

申请号：US16465515

申请日：2016-12-30

Applicant: Intel IP Corporation

Inventor： YAIR DGANI ,  Michael Kerner ,  Elan Banin ,  Nati Dinur ,  Gil Horovitz ,  Rotem Banin

IPC: H03L7/081 ,  H03L7/093 ,  H03L7/099 ,  H04L7/033

Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.