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    DPLL with adjustable delay in integer operation mode
    2.
    发明授权
    DPLL with adjustable delay in integer operation mode 有权

    公开(公告)号：US10686451B2

    公开(公告)日：2020-06-16

    申请号：US16465515

    申请日：2016-12-30

    Applicant: Intel IP Corporation

    Inventor： Yair Dgani ,  Michael Kerner ,  Elan Banin ,  Nati Dinur ,  Gil Horovitz ,  Rotem Banin

    IPC: H03L7/081 ,  H04L7/033 ,  H03L7/099 ,  H03L7/093

    Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

    PHASE SYNCHRONIZATION BETWEEN TWO PHASE LOCKED LOOPS
    3.
    发明申请
    PHASE SYNCHRONIZATION BETWEEN TWO PHASE LOCKED LOOPS 审中-公开

    公开(公告)号：US20180375519A1

    公开(公告)日：2018-12-27

    申请号：US15634183

    申请日：2017-06-27

    Applicant: Intel IP Corporation

    Inventor： Michael Kerner ,  Elan Banin ,  Yair Dgani ,  Evgeny Shumaker ,  Danniel Nahmanny ,  Gil Horovitz

    IPC: H03L7/087

    Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

    DPLL WITH ADJUSTABLE DELAY IN INTEGER OPERATION MODE
    4.
    发明申请
    DPLL WITH ADJUSTABLE DELAY IN INTEGER OPERATION MODE 审中-公开

    公开(公告)号：US20200067513A1

    公开(公告)日：2020-02-27

    申请号：US16465515

    申请日：2016-12-30

    Applicant: Intel IP Corporation

    Inventor： YAIR DGANI ,  Michael Kerner ,  Elan Banin ,  Nati Dinur ,  Gil Horovitz ,  Rotem Banin

    IPC: H03L7/081 ,  H03L7/093 ,  H03L7/099 ,  H04L7/033

    Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

    Reference signal path for clock generation with an injection locked multiplier (ILM)
    5.
    发明授权
    Reference signal path for clock generation with an injection locked multiplier (ILM) 有权

    公开(公告)号：US10418942B2

    公开(公告)日：2019-09-17

    申请号：US15171373

    申请日：2016-06-02

    Applicant: Intel IP Corporation

    Inventor： Igal Yehuda Kushnir ,  Gil Horovitz ,  Ronen Kronfeld ,  Sarit Zur

    IPC: H03B19/00 ,  H03B19/14 ,  H04L7/02 ,  H03L7/24

    Abstract: Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.

    Deterministic jitter removal using a closed loop digital-analog mechanism
    10.
    发明授权
    Deterministic jitter removal using a closed loop digital-analog mechanism 有权

    公开(公告)号：US09923563B1

    公开(公告)日：2018-03-20

    申请号：US15389520

    申请日：2016-12-23

    Applicant: Intel IP Corporation

    Inventor： Gil Horovitz ,  Elan Banin ,  Igal Kushnir ,  Aryeh Farber ,  Ran Krichman ,  Ofir Degani ,  Rotem Banin

    IPC: H03L7/08

    CPC classification number: H03L7/08 ,  H03K5/1565 ,  H03L7/0805 ,  H03L7/085 ,  H03L2207/10

    Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.

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