-
公开(公告)号：US10573387B2
公开(公告)日：2020-02-25
申请号：US16288556
申请日：2019-02-28
发明人： Masatoshi Ishii , Nobuyuki Ohba , Atsuya Okazaki
摘要： A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.
-
公开(公告)号：US10445640B1
公开(公告)日：2019-10-15
申请号：US16035188
申请日：2018-07-13
发明人： Megumi Ito , Masatoshi Ishii , Atsuya Okazaki
摘要： A computer-implemented method is provided for refreshing cells in a Non-Volatile Memory (NVM)-based neuromorphic circuit wherein synapses are each composed of a respective cell pair formed from a respective Gp cell and a respective Gm cell of the cells. The method includes randomly selecting multiple neurons and reading a Gp conductance and a Gm conductance of any of the synapses connected to the multiple neurons. The method further includes selecting any of the synapses connected to the selected multiple neurons for which any of the Gp conductance or the Gm conductance have reached a maximum conductance. The method also includes resetting the Gp cell and Gm cell of the selected synapses, and setting, at most, one of the Gp cell and Gm cell of each of the selected synapses to recover an effective total weight of each of the selected synapses.
-
公开(公告)号：US10339444B2
公开(公告)日：2019-07-02
申请号：US15411034
申请日：2017-01-20
摘要： A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.
-
公开(公告)号：US20180004666A1
公开(公告)日：2018-01-04
申请号：US15704551
申请日：2017-09-14
发明人： Nobuyuki Ohba , Atsuya Okazaki
IPC分类号： G06F12/0831 , G06F12/0842 , G06F12/0815 , G06F12/084
CPC分类号： G06F12/0831 , G06F12/0815 , G06F12/084 , G06F12/0842 , G06F2212/1056 , G06F2212/2542 , G06F2212/306 , G06F2212/62 , G06F2212/621
摘要： A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.
-
公开(公告)号：US20150331797A1
公开(公告)日：2015-11-19
申请号：US14700808
申请日：2015-04-30
发明人： Nobuyuki Ohba , Atsuya Okazaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0815 , G06F12/084 , G06F12/0842 , G06F2212/1056 , G06F2212/2542 , G06F2212/306 , G06F2212/62 , G06F2212/621
摘要： A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.
-
公开(公告)号：US09066289B2
公开(公告)日：2015-06-23
申请号：US13890338
申请日：2013-05-09
IPC分类号： H04J3/06 , H04W56/00 , H04L12/721 , H04W40/02 , H04W40/06
CPC分类号： H04W56/00 , H04J3/0658 , H04L45/40 , H04W40/02 , H04W40/06
摘要： A system including multiple nodes performing radio communication, wherein each node stores routing information, uses it to determine a transmission path, and performs cut-through transmission by transmitting and receiving packets to and from a node on the determined path through transmission and reception radio waves given a directivity by controlling their phases. In the system, time synchronization and transmission and reception of packet communication records are performed during a certain time period by carrying out the cut-through transmission while controlling phases of the radio waves so that all of the nodes form one or more closed loops. The node transmits and receives packets in accordance with routing information and a time frame assigned to each of the nodes as a time when each node is allowed to transmit and receive a packet, updates the routing information, and shares it with each node.
摘要翻译： 一种包括执行无线电通信的多个节点的系统，其中每个节点存储路由信息，使用它来确定传输路径，并且通过发送和接收无线电波通过在确定的路径上的节点发送和接收分组来执行直通传输 通过控制它们的阶段给出方向性。 在该系统中，通过在控制无线电波的相位的同时执行直通传输，使得所有节点形成一个或多个闭环，在一定时间段内执行分组通信记录的时间同步和发送和接收。 节点根据路由信息和分配给每个节点的时间帧发送和接收分组，作为允许每个节点发送和接收分组的时间，更新路由信息，并与每个节点共享。
-
公开(公告)号：US20140075250A1
公开(公告)日：2014-03-13
申请号：US14038906
申请日：2013-09-27
IPC分类号： G06F11/07
CPC分类号： G11C8/18 , G06F11/073 , G06F11/076 , G06F11/30 , G06F11/3037 , G06F11/3075 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.
-
公开(公告)号：US11763139B2
公开(公告)日：2023-09-19
申请号：US15875604
申请日：2018-01-19
IPC分类号： G06N3/049 , G06N3/065 , G06N3/08 , G06N3/088 , G11C13/00 , G06N3/084 , G11C29/02 , H10N70/20 , G11C11/54
CPC分类号： G06N3/049 , G06N3/065 , G06N3/08 , G06N3/084 , G06N3/088 , G11C11/54 , G11C13/0002 , G11C13/003 , G11C29/028 , H10N70/231 , G11C2213/77
摘要： A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.
-
公开(公告)号：US20230046980A1
公开(公告)日：2023-02-16
申请号：US17399147
申请日：2021-08-11
发明人： Takeo Yasuda , Atsuya Okazaki
摘要： A computer-implemented method for processing signals is provided including advantageously generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, executing a multiply and accumulate (MAC) operation with the memory access signal, and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).
-
公开(公告)号：US11087811B1
公开(公告)日：2021-08-10
申请号：US16885618
申请日：2020-05-28
发明人： Akiyo Iwashina , Atsuya Okazaki , Takeo Yasuda
摘要： An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.
-
-
-
-
-
-
-
-
-
搜索结果
46 条记录 (耗时 0.021 秒)
