公开(公告)号：US20210118854A1

公开(公告)日：2021-04-22

申请号：US17135474

申请日：2020-12-28

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Fee Li Lie ,  Kevin Winstel ,  Ravi K. Bonam ,  Iqbal Rashid Saraf ,  Dario Goldfarb ,  Daniel Corliss ,  Dinesh Gupta

IPC: H01L25/065 ,  H01L23/48 ,  H01L29/16 ,  H01L23/46 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

公开(公告)号：US20200294968A1

公开(公告)日：2020-09-17

申请号：US16351757

申请日：2019-03-13

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Fee Li Lie ,  Kevin Winstel ,  Ravi K. Bonam ,  Iqbal Rashid Saraf ,  Dario Goldfarb ,  Daniel Corliss ,  Dinesh Gupta

IPC: H01L25/065 ,  H01L23/48 ,  H01L29/16 ,  H01L23/46 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

公开(公告)号：US11462512B2

公开(公告)日：2022-10-04

申请号：US17135474

申请日：2020-12-28

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Fee Li Lie ,  Kevin Winstel ,  Ravi K. Bonam ,  Iqbal Rashid Saraf ,  Dario Goldfarb ,  Daniel Corliss ,  Dinesh Gupta

IPC: H01L25/065 ,  H01L23/48 ,  H01L29/16 ,  H01L23/46 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

公开(公告)号：US10937764B2

公开(公告)日：2021-03-02

申请号：US16351757

申请日：2019-03-13

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Fee Li Lie ,  Kevin Winstel ,  Ravi K. Bonam ,  Iqbal Rashid Saraf ,  Dario Goldfarb ,  Daniel Corliss ,  Dinesh Gupta

IPC: H01L25/065 ,  H01L23/48 ,  H01L29/16 ,  H01L23/46 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

公开(公告)号：US20190267234A1

公开(公告)日：2019-08-29

申请号：US16404312

申请日：2019-05-06

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Dario Goldfarb ,  Nelson Felix ,  Daniel Corliss ,  Rudy J. Wojtecki

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/033 ,  G03F7/09 ,  G03F7/20 ,  G03F7/26

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

公开(公告)号：US20190163857A1

公开(公告)日：2019-05-30

申请号：US15827618

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Corliss ,  Derren N. Dunn ,  Michael A. Guillorn ,  Shawn P. Fetterolf

IPC: G06F17/50 ,  H01L21/027 ,  H01L23/58

Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

公开(公告)号：US10921716B1

公开(公告)日：2021-02-16

申请号：US16595862

申请日：2019-10-08

Applicant: International Business Machines Corporation

Inventor： Christopher Robinson ,  Daniel Corliss

IPC: G03F7/20 ,  G03F7/32 ,  G03F7/38

Abstract: Methods for determining unintentional exposure dose such as flare or out-of-band radiation of a lithography tool are provided. The methods generally include performing a series of open frame exposures with the lithography tool on a substrate having a photoresist therein to produce a primary array of controlled exposure dose blocks in the photoresist. Secondary exposure blocks are embedded within the primary array. The resultant open frame images are scanned with oblique light and the light scattered from the substrate surface captured. A haze map is created from a background signal of the captured scattered light data and converted to a graphical image file. Analyzing the graphical image file can be used to correlate any localized changes in the effective dose of the primary exposure array to the impact of secondary exposure blocks to characterize flare or out-of-band radiation associated with the exposure dose.

公开(公告)号：US10650111B2

公开(公告)日：2020-05-12

申请号：US15827618

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Corliss ,  Derren N. Dunn ,  Michael A. Guillorn ,  Shawn P. Fetterolf

IPC: G06F17/50 ,  H01L23/58 ,  H01L21/027

Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

公开(公告)号：US20190189428A1

公开(公告)日：2019-06-20

申请号：US15846942

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Dario Goldfarb ,  Nelson Felix ,  Daniel Corliss ,  Rudy J. Wojtecki

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/20 ,  G03F7/09 ,  G03F7/26

CPC classification number: H01L21/0274 ,  G03F7/094 ,  G03F7/2004 ,  G03F7/26 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/32139

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

公开(公告)号：US11288429B2

公开(公告)日：2022-03-29

申请号：US16732824

申请日：2020-01-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Corliss ,  Derren N. Dunn ,  Michael A. Guillorn ,  Shawn P. Fetterolf

IPC: G06F30/34 ,  H01L23/58 ,  H01L21/027 ,  G06F30/36 ,  G06F30/30 ,  G06F30/39 ,  G06F30/333 ,  G06F115/10 ,  G06F117/06

Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.