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    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
    1.
    发明申请
    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
    用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构

    公开(公告)号：US20040063277A1

    公开(公告)日：2004-04-01

    申请号：US10260085

    申请日：2002-09-27

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer JR. ,  Padraic Shafer ,  Joseph F. Shepard JR.

    IPC分类号： H01L021/8242

    CPC分类号： H01L29/66181 ,  H01L21/3144 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10864 ,  H01L27/10867

    摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

    摘要翻译： 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。

    VERTICAL HARD MASK
    2.
    发明申请
    VERTICAL HARD MASK 失效
    垂直硬面膜

    公开(公告)号：US20040048441A1

    公开(公告)日：2004-03-11

    申请号：US10241225

    申请日：2002-09-10

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Infineon Technologies North America Corp.

    发明人： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Kenneth T. Settlemyer JR. ,  Helmut Horst Tews

    IPC分类号： H01L021/20

    CPC分类号： H01L27/1087

    摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

    摘要翻译： 在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在 下部。

    A 3-D MICROELECTRONIC STRUCTURE INCLUDING A VERTICAL THERMAL NITRIDE MASK
    3.
    发明申请
    A 3-D MICROELECTRONIC STRUCTURE INCLUDING A VERTICAL THERMAL NITRIDE MASK 审中-公开
    一个三维微电子结构，包括一个垂直的硝酸盐掩蔽

    公开(公告)号：US20030107111A1

    公开(公告)日：2003-06-12

    申请号：US10013797

    申请日：2001-12-10

    申请人： International Business Machines Corporation

    发明人： Oleg Gluschenkov ,  Michael P. Chudzik ,  Rajarao Jammy ,  Christopher C. Parks ,  Kenneth T. Settlemyer JR. ,  Radhika Srinivasan ,  Kathryn H. Varian

    IPC分类号： H01L023/58

    CPC分类号： H01L27/1087 ,  H01L21/3185

    摘要： A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

    摘要翻译： 提供了一种3D微电子结构，其包括其中存在至少一个开口的基底，所述至少一个开口具有延伸到公共底壁的侧壁; 以及存在于开口的每个侧壁的至少上部的热氮化物层。 还提供了一种用于制造上述3D微电子结构的方法。 具体地，该方法包括在形成于基板中的开口的每个侧壁的至少上部选择性地形成热氮化物层的步骤。

    Method of drying substrates
    4.
    发明申请
    Method of drying substrates 失效
    干燥基材的方法

    公开(公告)号：US20020112369A1

    公开(公告)日：2002-08-22

    申请号：US09784876

    申请日：2001-02-16

    申请人： International Business Machines Corporation

    发明人： Russell H. Arndt ,  Glenn Walton Gale ,  James Willard Hannah ,  Kenneth T. Settlemyer JR.

    IPC分类号： F26B003/00

    CPC分类号： H01L21/02052

    摘要： A method of removing water from the surface of a silicon wafer or other substrate subjected to wet processing which includes a step of water rinsing. In this method a silicon wafer whose surface includes liquid water is disposed in an atmosphere saturated with water vapor. The water vapor is removed from the surface of the silicon wafer by a stream of water-saturated gas. Upon removal of liquid water from the surface of the silicon wafer the water vapor in the water vapor saturated atmosphere is removed by evaporation.

    摘要翻译： 从经过湿法处理的硅晶片或其他基板的表面除去水的方法，其包括水洗步骤。 在该方法中，表面包含液态水的硅晶片设置在饱和水蒸汽的气氛中。 通过水饱和气流从硅晶片的表面除去水蒸汽。 在从硅晶片的表面去除液态水时，通过蒸发除去水蒸汽饱和气氛中的水蒸汽。

    FILLING HIGH ASPECT RATIO ISOLATION STRUCTURES WITH POLYSILAZANE BASED MATERIAL
    5.
    发明申请
    FILLING HIGH ASPECT RATIO ISOLATION STRUCTURES WITH POLYSILAZANE BASED MATERIAL 失效
    用基于聚硅氧烷的材料填充高比例分离结构

    公开(公告)号：US20040248374A1

    公开(公告)日：2004-12-09

    申请号：US10250092

    申请日：2003-06-03

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemyer JR. ,  Padraic C. Shafer

    IPC分类号： H01L021/76

    CPC分类号： H01L21/76229

    摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

    摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。