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17 条记录 (耗时 0.018 秒)

    Method of enhancing surface reactions by local resonant heating
    2.
    发明申请
    Method of enhancing surface reactions by local resonant heating 审中-公开
    通过局部谐振加热增强表面反应的方法

    公开(公告)号：US20040112863A1

    公开(公告)日：2004-06-17

    申请号：US10320852

    申请日：2002-12-16

    申请人： International Business Machines Corporation

    发明人： Bomy A. Chen ,  Rajarao Jammy ,  Siddhartha Panda ,  Richard S. Wise

    IPC分类号： C23F001/00

    CPC分类号： H01L21/32136 ,  C23C16/481 ,  C23C16/507 ,  C23F4/00 ,  H01J37/321 ,  H01J2237/2001 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/31612

    摘要： Methods and an apparatus for processing a substrate. A first method comprising: reacting a layer formed on the substrate with a plasma to form a reaction product layer; and simultaneously exposing the reaction product layer to resonant radiation to volatilize the reaction product layer. A second method comprising: performing a plasma enhanced chemical vapor deposition to deposit a precursor layer on a substrate; and simultaneously heating the precursor layer by exposure of the precursor layer to resonant radiation to convert the precursor layer to a deposited layer.

    摘要翻译： 用于处理衬底的方法和装置。 一种第一方法，包括：使形成在所述衬底上的层与等离子体反应以形成反应产物层; 并同时将反应产物层暴露于共振辐射以挥发反应产物层。 第二种方法包括：执行等离子体增强化学气相沉积以在衬底上沉积前体层; 并且通过将前体层暴露于共振辐射同时加热前体层，以将前体层转化为沉积层。

    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
    3.
    发明申请
    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
    用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构

    公开(公告)号：US20040063277A1

    公开(公告)日：2004-04-01

    申请号：US10260085

    申请日：2002-09-27

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer JR. ,  Padraic Shafer ,  Joseph F. Shepard JR.

    IPC分类号： H01L021/8242

    CPC分类号： H01L29/66181 ,  H01L21/3144 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10864 ,  H01L27/10867

    摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

    摘要翻译： 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。

    Dram trench capacitor
    4.
    发明申请
    Dram trench capacitor 失效
    电容沟槽电容

    公开(公告)号：US20010039087A1

    公开(公告)日：2001-11-08

    申请号：US09764656

    申请日：2001-01-17

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Rajarao Jammy ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L021/8242 ,  H01L021/20

    CPC分类号： H01L27/10861

    摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.

    摘要翻译： 本发明涉及制造半导体存储器结构，特别是深沟槽半导体存储器件的工艺，其中将温度敏感的高介电常数材料并入电容器的存储节点中。 具体地，本发明描述了在高温浅沟槽隔离和栅极导体处理之后形成深沟槽存储电容器的工艺。 该过程允许将温度敏感的高介电常数材料并入电容器结构中而不会导致该材料的分解。 此外，本发明的方法限制了埋层扩散的程度，从而改善阵列MOSFET的电特性。

    METHOD FOR SURFACE ROUGHNESS ENHANCEMENT IN SEMICONDUCTOR CAPACITOR MANUFACTURING
    5.
    发明申请
    METHOD FOR SURFACE ROUGHNESS ENHANCEMENT IN SEMICONDUCTOR CAPACITOR MANUFACTURING 失效
    半导体电容器制造中表面粗糙度增强的方法

    公开(公告)号：US20030114005A1

    公开(公告)日：2003-06-19

    申请号：US10016075

    申请日：2001-12-13

    申请人： International Business Machines Corporation

    发明人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

    IPC分类号： H01L021/20

    CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L28/90

    摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

    摘要翻译： 公开了一种用于增加半导体器件中原始表面的表面积的方法。 在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。 然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。 因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

    FILLING HIGH ASPECT RATIO ISOLATION STRUCTURES WITH POLYSILAZANE BASED MATERIAL
    7.
    发明申请
    FILLING HIGH ASPECT RATIO ISOLATION STRUCTURES WITH POLYSILAZANE BASED MATERIAL 失效
    用基于聚硅氧烷的材料填充高比例分离结构

    公开(公告)号：US20040248374A1

    公开(公告)日：2004-12-09

    申请号：US10250092

    申请日：2003-06-03

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemyer JR. ,  Padraic C. Shafer

    IPC分类号： H01L021/76

    CPC分类号： H01L21/76229

    摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

    摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

    Reduction of polysilicon stress in trench capacitors
    9.
    发明申请
    Reduction of polysilicon stress in trench capacitors 失效

    公开(公告)号：US20030013259A1

    公开(公告)日：2003-01-16

    申请号：US09904612

    申请日：2001-07-13

    申请人： International Business Machines Corporation

    发明人： Dureseti Chidambarrao ,  Rajarao Jammy ,  Jack A. Mandelman

    IPC分类号： H01L021/8242 ,  H01L021/20

    CPC分类号： H01L27/10867

    摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.