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公开(公告)号：US20220413911A1
公开(公告)日：2022-12-29
申请号：US17362189
申请日：2021-06-29
发明人： Brian W. Thompto , Michael Joseph Genden , Tharunachalam Pindicura , Phillip G. Williams , Kent Li , Nir Segev , Mehul Patel
摘要： A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.
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公开(公告)号：US10048963B2
公开(公告)日：2018-08-14
申请号：US15161461
申请日：2016-05-23
摘要： Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.
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公开(公告)号：US11886883B2
公开(公告)日：2024-01-30
申请号：US17458407
申请日：2021-08-26
发明人： Nicholas R. Orzol , Mehul Patel , Dung Q. Nguyen , Brian D. Barrick , Richard J. Eickemeyer , John B Griswell, Jr. , Balaram Sinharoy , Brian W. Thompto , Ophir Erez
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/30058 , G06F9/30069
摘要： A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.
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公开(公告)号：US20230068640A1
公开(公告)日：2023-03-02
申请号：US17458407
申请日：2021-08-26
发明人： Nicholas R. Orzol , Mehul Patel , Dung Q. Nguyen , Brian D. Barrick , Richard J. Eickemeyer , John B. Griswell, JR. , Balaram Sinharoy , Brian W. Thompto , Ophir Erez
摘要： A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.
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公开(公告)号：US20230060910A1
公开(公告)日：2023-03-02
申请号：US17410230
申请日：2021-08-24
发明人： Nicholas R. Orzol , Mehul Patel , Dung Q. Nguyen , Brian D. Barrick , Richard J. Eickemeyer , John B. Griswell, JR. , Balaram Sinharoy , Brian W. Thompto , Ophir Erez
摘要： A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.
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公开(公告)号：US10528353B2
公开(公告)日：2020-01-07
申请号：US15162998
申请日：2016-05-24
发明人： David S. Levitan , Mehul Patel
摘要： Methods and apparatus for generating a mask vector for determining a processor instruction address using an instruction tag (ITAG) in a multi-slice processor including receiving a first ITAG value and an interrupt ITAG value; generating the mask vector divided into mask sections comprising a plurality of elements with unset flags; for each mask section: if the mask section comprises the first ITAG value, setting a flag of an element in the mask section corresponding to the first ITAG value; if the mask section comprises the interrupt ITAG value, setting a flag of an element in the mask section corresponding to the interrupt ITAG value; setting each flag of each element in the mask vector between the element in the mask vector corresponding to the first ITAG value and the element in the mask vector corresponding to the interrupt ITAG value; and providing the mask vector to an instruction fetch unit.
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公开(公告)号：US20230063079A1
公开(公告)日：2023-03-02
申请号：US17410223
申请日：2021-08-24
发明人： Mehul Patel , Nicholas R. Orzol , Dung Q. Nguyen , Balaram Sinharoy , Richard J. Eickemeyer , John B. Griswell, Jr. , Brian W. Thompto
摘要： A computer processor includes an instruction pipeline configured to dispatch a plurality of branch-to-count (BCNT) instructions and an instruction fetch unit (IFU). The IFU is configured to execute an instruction loop for fetching a targeted number of BCNT instructions from the instruction pipeline and to monitor a loop counter that counts a number of fetched BCNT instructions that are actually fetched from the instruction pipeline in response to executing the instruction loop. The IFU resolves a final BCNT instruction included in the instruction loop in response to the number of fetched BCNT instructions reaching a target loop count value.
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公开(公告)号：US10248555B2
公开(公告)日：2019-04-02
申请号：US15168434
申请日：2016-05-31
摘要： Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.
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公开(公告)号：US11663013B2
公开(公告)日：2023-05-30
申请号：US17410230
申请日：2021-08-24
发明人： Nicholas R. Orzol , Mehul Patel , Dung Q. Nguyen , Brian D. Barrick , Richard J. Eickemeyer , John B. Griswell, Jr. , Balaram Sinharoy , Brian W. Thompto , Ophir Erez
CPC分类号： G06F9/3838 , G06F9/30036 , G06F9/30043 , G06F9/3844
摘要： A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.
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公开(公告)号：US10528347B2
公开(公告)日：2020-01-07
申请号：US15980874
申请日：2018-05-16
摘要： Executing system call vectored (SCV) instructions in a multi-slice processor including receiving, by an instruction fetch unit, a SCV instruction, wherein the SCV instruction is a system call from an operating system; sending the SCV instruction to a branch issue queue; determining, by the branch issue queue, that the SCV instruction is next-to-complete; issuing the SCV instruction to a branch resolution unit; and executing the SCV instruction by the branch resolution unit.
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