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公开(公告)号：US11709676B2
公开(公告)日：2023-07-25
申请号：US17406186
申请日：2021-08-19
发明人： Steven J. Battle , Brian D. Barrick , Dung Q. Nguyen , Richard J. Eickemeyer , John B. Griswell, Jr. , Balaram Sinharoy , Brian W. Thompto , Tu-An T. Nguyen
CPC分类号： G06F9/30058 , G06F9/30021 , G06F9/3857 , G06F9/3861
摘要： Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.
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公开(公告)号：US11663013B2
公开(公告)日：2023-05-30
申请号：US17410230
申请日：2021-08-24
发明人： Nicholas R. Orzol , Mehul Patel , Dung Q. Nguyen , Brian D. Barrick , Richard J. Eickemeyer , John B. Griswell, Jr. , Balaram Sinharoy , Brian W. Thompto , Ophir Erez
CPC分类号： G06F9/3838 , G06F9/30036 , G06F9/30043 , G06F9/3844
摘要： A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.
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公开(公告)号：US20230063079A1
公开(公告)日：2023-03-02
申请号：US17410223
申请日：2021-08-24
发明人： Mehul Patel , Nicholas R. Orzol , Dung Q. Nguyen , Balaram Sinharoy , Richard J. Eickemeyer , John B. Griswell, Jr. , Brian W. Thompto
摘要： A computer processor includes an instruction pipeline configured to dispatch a plurality of branch-to-count (BCNT) instructions and an instruction fetch unit (IFU). The IFU is configured to execute an instruction loop for fetching a targeted number of BCNT instructions from the instruction pipeline and to monitor a loop counter that counts a number of fetched BCNT instructions that are actually fetched from the instruction pipeline in response to executing the instruction loop. The IFU resolves a final BCNT instruction included in the instruction loop in response to the number of fetched BCNT instructions reaching a target loop count value.
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4.发明授权公开(公告)号：US11520591B2
公开(公告)日：2022-12-06
申请号：US16832845
申请日：2020-03-27
IPC分类号： G06F9/38
摘要： Processing data in an information handling system is disclosed that includes: in response to an event that triggers a flushing operation, calculate a finish ratio, wherein the finish ratio is a number of finished operations to a number of at least one of the group consisting of in-flight instructions, instructions pending in a processor pipeline, instructions issued to an issue queue, and instructions being processed in a processor execution unit; compare the calculated finish ratio to a threshold; and if the finish ratio is greater than the threshold, then do not perform the flushing operation. Also disclosed is moving the flush point.
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公开(公告)号：US11868773B2
公开(公告)日：2024-01-09
申请号：US17569951
申请日：2022-01-06
发明人： Steven J. Battle , Brian D. Barrick , Dung Q. Nguyen , Richard J. Eickemeyer , John B. Griswell, Jr. , Balaram Sinharoy , Brian W. Thompto , Tu-An T. Nguyen
CPC分类号： G06F9/30058 , G06F9/30021 , G06F9/30043 , G06F9/3842 , G06F9/3856
摘要： A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.
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公开(公告)号：US11537402B1
公开(公告)日：2022-12-27
申请号：US17305734
申请日：2021-07-14
发明人： Brian D. Barrick , Bryan Lloyd , Dung Q. Nguyen , Brian W. Thompto , Edmund Joseph Gieske , John B. Griswell, Jr.
摘要： A method for operation of a processor core is provided. First instruction data is consulted to determine whether a second instruction has execution data that matches the first instruction data. The first instruction data is from a first instruction. In response to determining that the second instruction has execution data that matches the first instruction data, prior data is copied into the second instruction. The first instruction depends on the prior data. After receiving an availability indication of the prior data, both the first instruction and the second instruction are woken for execution, without requiring execution of the first instruction before waking of the second instruction. The second instruction is executed by using the prior data as a skip of the first instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.
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公开(公告)号：US11080060B2
公开(公告)日：2021-08-03
申请号：US16391814
申请日：2019-04-23
IPC分类号： G06F9/32 , G06F9/30 , G06F9/38 , G06F12/0864
摘要： Managing application execution by receiving a store instruction, including a store instruction itag and store instruction address, creating a hash of the store instruction address, receiving a load instruction and matching a hash of a store instruction address associated with the load instruction with the hash of the store instruction address associated with the store instruction. The store instruction itag is sent to an instruction sequencing unit (ISU). The ISU delays execution of the load instruction according to the received itag.
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公开(公告)号：US11847458B2
公开(公告)日：2023-12-19
申请号：US17366244
申请日：2021-07-02
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/3844
摘要： Methods and systems for determining a priority of a threads is described. A processor can execute branch instructions of the thread. The processor can predict branch instruction outcomes of the branch instructions of the thread. The processor can increment a misprediction count of the thread in response to an actual execution of a branch instruction of the thread being different from a corresponding branch instruction prediction outcome of the thread. The processor can determine the priority of the thread based on the misprediction count of the thread.
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公开(公告)号：US11226817B2
公开(公告)日：2022-01-18
申请号：US16508671
申请日：2019-07-11
IPC分类号： G06F9/30 , G06F9/38 , G06F12/1018 , G06F12/0862
摘要： A set of dependence relationships in a set of program instructions is detected by a processor. The set of dependence relationships comprises a first load instruction to load a first data object and a second load instruction to load a second data object from a second address that is provided by address data within the first data object. The processor identifies a number of dependence instances in the set of dependence relationships and determines that the number is over a pattern threshold. The processor sends an enhanced load request to a memory controller. The enhanced load request comprises instructions to load the first data object from a first address on a physical page, locate address data in the first data object based on a memory offset, load the second data object from a second address in the address data, and transmit the first and second data objects to the processor.
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公开(公告)号：US11182164B1
公开(公告)日：2021-11-23
申请号：US16936924
申请日：2020-07-23
摘要： Support for instruction fusion is provided. An indication whether an instruction is a paired instruction is received from an instruction decoder. Based on the indication, one dispatch slot or a paired dispatch slot is allocated in the instruction dispatcher queue. A mapper converts logical addresses of sources and targets of the instruction to physical addresses. Either one issue slot or a paired issue slot is allocated in an issue queue based on the indication from the instruction decoder. The instruction execution environment is loaded into the issue queue and issued to an execution unit.
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