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公开(公告)号：US09741485B2
公开(公告)日：2017-08-22
申请号：US14823113
申请日：2015-08-11
Applicant: International Business Machines Corporation
Inventor： Pinping Sun , Chengwen Pei , Zheng Xu
CPC classification number: H01F27/362 , H01F17/0013 , H01F27/2804 , H01F27/2871 , H01F27/289 , H01F41/041 , H01F2017/008 , H01F2027/2809 , H01L23/60 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.
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公开(公告)号：US20140139295A1
公开(公告)日：2014-05-22
申请号：US13681446
申请日：2012-11-20
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Pinping Sun , Chengwen Pei
IPC: H03B1/02
CPC classification number: H03B5/1212 , H03B1/02 , H03B5/1228 , H03B5/124
Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) is provided, in which the body of each transistor within a pair of cross-coupled transistors is coupled to the gate of the same transistor through a resistor. The body transconductance is employed to enhance the negative resistance of the cross-coupled pair of transistors. At the same time, a forward body bias voltage reduces the threshold voltage of the cross-coupled pair to allow the VCO to operate at a low power supply voltage. Further, the resistor connected between the body and the drain of each transistor voids the leakage in the substrate, and thus, reduces power consumption of the VCO further. This VCO provides low power operation with enhanced figure of merit without employing any extra inductors besides the inductors that are part of the LC tank.
Abstract translation: 提供了一种增强的负电阻压控振荡器（VCO），其中一对交叉耦合晶体管内的每个晶体管的主体通过电阻器耦合到同一晶体管的栅极。 采用体内跨导来增强交叉耦合的晶体管对的负电阻。 同时，正向体偏置电压降低了交叉耦合对的阈值电压，以允许VCO在低电源电压下工作。 此外，连接在每个晶体管的主体和漏极之间的电阻器使得衬底中的漏电，从而进一步降低了VCO的功耗。 该VCO提供具有增强品质因数的低功率操作，而不需要除LC电容器一部分的电感器之外的任何额外的电感器。
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公开(公告)号：US09218903B2
公开(公告)日：2015-12-22
申请号：US14037415
申请日：2013-09-26
Applicant: International Business Machines Corporation
Inventor： Pinping Sun , Chengwen Pei , Zheng Xu
CPC classification number: H01F27/362 , H01F17/0013 , H01F27/2804 , H01F27/2871 , H01F27/289 , H01F41/041 , H01F2017/008 , H01F2027/2809 , H01L23/60 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.
Abstract translation: 形成在半导体结构内的可重构多叠层电感器可以包括位于半导体结构的第一金属层内的第一电感结构，位于第一金属层内的第一接地屏蔽结构，其与第一电感器 结构，以及位于半导体结构的第二金属层内的第二电感结构，由此第二电感结构电耦合到第一电感结构。 位于第二金属层内的第二接地屏蔽结构与第二电感器结构电隔离并在周向上限定第二电感结构，由此第一和第二电感器基于第一接地屏蔽结构产生第一电感值，并且第二接地屏蔽结构耦合到地 并且第一和第二电感器基于第一接地屏蔽结构和电浮置的第二接地屏蔽结构产生第二电感值。
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公开(公告)号：US20140368286A1
公开(公告)日：2014-12-18
申请号：US13916612
申请日：2013-06-13
Applicant: International Business Machines Corporation
Inventor： Pinping Sun
IPC: H03B5/24
CPC classification number: H03B5/24 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B2200/0082 , H03B2200/009
Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) circuit is provided, in which a parallel connection of a capacitor and a resistor configured to provide frequency-dependent transconductance is present across source nodes of a first pair of field effect transistors in which gate nodes and drain nodes are cross-coupled. The source nodes of the first pair of field effect transistors are electrically shorted to drain nodes of a second pair of field effect transistors of which the gate nodes are electrically shorted to the gate nodes of the first pair of field effect transistors. The parallel connection of the capacitor and the resistor includes a parallel connection of a capacitor and a resistor such that the net transconductance of the first pair of field effect transistors is less at low frequencies where thermal noise and flicker noise are dominant part of the phase noise than at the operational frequency range.
Abstract translation: 提供了一种增强的负电阻压控振荡器（VCO）电路，其中电容器和被配置为提供频率相关跨导的电阻器的并联连接存在于第一对场效应晶体管的源节点之间，其中栅极节点和 排水节点是交叉耦合的。 第一对场效应晶体管的源极节点与第二对场效应晶体管的漏极节点电短路，其栅极节点与第一对场效应晶体管的栅极节点电短路。 电容器和电阻器的并联连接包括电容器和电阻器的并联连接，使得第一对场效应晶体管的净跨导在低频处较小，其中热噪声和闪烁噪声是相位噪声的主要部分 比在工作频率范围。
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公开(公告)号：US20150348919A1
公开(公告)日：2015-12-03
申请号：US14823113
申请日：2015-08-11
Applicant: International Business Machines Corporation
Inventor： Pinping Sun , Chengwen Pei , Zheng Xu
CPC classification number: H01F27/362 , H01F17/0013 , H01F27/2804 , H01F27/2871 , H01F27/289 , H01F41/041 , H01F2017/008 , H01F2027/2809 , H01L23/60 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.
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Patent Agency Ranking
公开(公告)号：US09024411B2
公开(公告)日：2015-05-05
申请号：US13964654
申请日：2013-08-12
Applicant: International Business Machines Corporation
Inventor： Junjun Li , Yan Zun Li , Chengwen Pei , Pinping Sun
IPC: H01L23/52 , H01L21/44 , H01L23/525 , H01L21/768
CPC classification number: H01L23/5256 , H01L21/76816 , H01L21/7682 , H01L21/76897 , H01L23/5283 , H01L23/5329 , H01L2924/0002 , H01L2924/00
Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.
Abstract translation: 有利地用作电子熔丝的三维（3d）限制导体和形成其的自对准方法。 通过在凸起结构上非电积层沉积电介质膜，可以在凸起结构之间形成可以为亚光刻的3d限制管。 与3d限制区域和随后的金属沉积相交的蚀刻孔填充3d限制区域并形成接触。 当凸起的结构是栅极时，熔丝元件可以位于线的中间（即在金属前电介质中）。 还描述了用于创建结构的其它方法。
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公开(公告)号：US20150303191A1
公开(公告)日：2015-10-22
申请号：US14257143
申请日：2014-04-21
Applicant: International Business Machines Corporation
Inventor： Kai D. Feng , Dan Moy , Chengwen Pei , Robert R. Robison , Pinping Sun , Richard A. Wachnik , Ping-Chuan Wang
CPC classification number: H01L27/0733 , H01L27/0629 , H01L27/0805 , H01L27/11206 , H01L29/66181 , H01L29/945
Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.
Abstract translation: 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。
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公开(公告)号：US09035708B2
公开(公告)日：2015-05-19
申请号：US13916612
申请日：2013-06-13
Applicant: International Business Machines Corporation
Inventor： Pinping Sun
CPC classification number: H03B5/24 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B2200/0082 , H03B2200/009
Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) circuit is provided, in which a parallel connection of a capacitor and a resistor configured to provide frequency-dependent transconductance is present across source nodes of a first pair of field effect transistors in which gate nodes and drain nodes are cross-coupled. The source nodes of the first pair of field effect transistors are electrically shorted to drain nodes of a second pair of field effect transistors of which the gate nodes are electrically shorted to the gate nodes of the first pair of field effect transistors. The parallel connection of the capacitor and the resistor includes a parallel connection of a capacitor and a resistor such that the net transconductance of the first pair of field effect transistors is less at low frequencies where thermal noise and flicker noise are dominant part of the phase noise than at the operational frequency range.
Abstract translation: 提供了一种增强的负电阻压控振荡器（VCO）电路，其中电容器和被配置为提供频率相关跨导的电阻器的并联连接存在于第一对场效应晶体管的源节点之间，其中栅极节点和 排水节点是交叉耦合的。 第一对场效应晶体管的源极节点与第二对场效应晶体管的漏极节点电短路，其栅极节点与第一对场效应晶体管的栅极节点电短路。 电容器和电阻器的并联连接包括电容器和电阻器的并联连接，使得第一对场效应晶体管的净跨导在低频处较小，其中热噪声和闪烁噪声是相位噪声的主要部分 比在工作频率范围。
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公开(公告)号：US20150097266A1
公开(公告)日：2015-04-09
申请号：US14047638
申请日：2013-10-07
Applicant: International Business Machines Corporation
Inventor： Junjun Li , Yan Zun Li , Chengwen Pei , Pinping Sun
IPC: H01L23/525 , H01L21/768
CPC classification number: H01L23/5256 , H01L21/7684 , H01L21/76877 , H01L23/62 , H01L2924/0002 , H01L2924/00
Abstract: An electronic fuse link with lower programming current for high performance and self-aligned methods of forming the same. The invention provides a horizontal e-fuse structure in the middle of the line. A reduced fuse link width is achieved by spacers on sides of pair of dummy or active gates, to create sub-lithographic dimension between gates with spacers to confine a fuse link. A reduced height in the third dimension on the fuse link achieved by etching the link, thereby creating a fuse link having a sub-lithographic size in all dimensions. The fuse link is formed over an isolation region to enhanced heating and aid fuse blow.
Abstract translation: 一种具有较低编程电流的电子熔断体，用于高性能和自对准的形成方法。 本发明在线路中间提供一个水平电子熔丝结构。 通过在一对虚拟或有源栅极的侧面上的间隔物实现降低的熔丝链接宽度，以在具有间隔物的栅极之间产生用于限制熔丝链路的亚光刻尺寸。 通过蚀刻链路在熔丝链上的第三维度上的高度减小，由此产生在所有尺寸上具有亚光刻尺寸的熔丝链。 熔断体形成在隔离区域上，以增强加热和帮助保险丝熔断。
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公开(公告)号：US20150084733A1
公开(公告)日：2015-03-26
申请号：US14037415
申请日：2013-09-26
Applicant: International Business Machines Corporation
Inventor： Pinping Sun , Chengwen Pei , Zheng Xu
CPC classification number: H01F27/362 , H01F17/0013 , H01F27/2804 , H01F27/2871 , H01F27/289 , H01F41/041 , H01F2017/008 , H01F2027/2809 , H01L23/60 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.
Abstract translation: 形成在半导体结构内的可重构多叠层电感器可以包括位于半导体结构的第一金属层内的第一电感结构，位于第一金属层内的第一接地屏蔽结构，其与第一电感器 结构，以及位于半导体结构的第二金属层内的第二电感结构，由此第二电感结构电耦合到第一电感结构。 位于第二金属层内的第二接地屏蔽结构与第二电感器结构电隔离并在周向上限定第二电感结构，由此第一和第二电感器基于第一接地屏蔽结构产生第一电感值，并且第二接地屏蔽结构耦合到地 并且第一和第二电感器基于第一接地屏蔽结构和电浮置的第二接地屏蔽结构产生第二电感值。
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