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公开(公告)号：US20240320477A1
公开(公告)日：2024-09-26
申请号：US18124055
申请日：2023-03-21
CPC分类号： G06N3/048 , G06F7/5443 , G06N3/065
摘要： Weights of a layer of an artificial neural network can be programmed on a crossbar array of resistive memory devices. The programmed weights can be calibrated to counteract fixed variability sources like CMOS variability by adjusting the programmed weights based on comparing the crossbar array's output with a target output. The crossbar array's output produced using the calibrated programmed weights can be input into a next crossbar array of resistive memory devices implementing a next layer of the artificial neural network to calibrate weights of the next layer of the artificial neural network programmed on the next crossbar array. The weights of the next layer of the artificial neural network programmed on the next crossbar array can be calibrated by adjusting the weights of the next layer based on comparing the next crossbar array's output with a next target output.
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公开(公告)号：US20240192921A1
公开(公告)日：2024-06-13
申请号：US18078212
申请日：2022-12-09
CPC分类号： G06F7/5443 , G06F17/18
摘要： Systems and methods for compensating multiply and accumulate (MAC) operations are described. A processor can send an input vector to a first portion of a memory device. The first portion can store synaptic weights of a trained artificial neural network (ANN). The processor can read a first result of a MAC operation performed on the input vector and the synaptic weights stored in the first portion. The processor can send an inverse of the input vector to a second portion of the memory device. The processor can read a second result of a MAC operation performed on the inverse of the input vector and an inverse of synaptic weights stored in the second portion. The processor can combine the first result and the second result to generate a final result. The final result can be a compensated version of the first result.
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公开(公告)号：US20240162889A1
公开(公告)日：2024-05-16
申请号：US17978161
申请日：2022-10-31
发明人： Charles Mackin , Pritish Narayanan
IPC分类号： H03K3/017 , H03K17/687
CPC分类号： H03K3/017 , H03K17/6871
摘要： A circuit comprises a first pulse-width modulator configured to generate a first pulse based on a first input, a second pulse-width modulator configured to generate a second pulse based on a second input, a first differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor, and a second differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor. A gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit, and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first and second pulse width modulators based on the first input and the second input.
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公开(公告)号：US11562240B2
公开(公告)日：2023-01-24
申请号：US16884128
申请日：2020-05-27
发明人： Hsinyu Tsai , Geoffrey Burr , Pritish Narayanan
摘要： Implementing a convolutional neural network (CNN) includes configuring a crosspoint array to implement a convolution layer in the CNN. Convolution kernels of the layer are stored in crosspoint devices of the array. Computations for the CNN are performed by iterating a set of operations for a predetermined number of times. The operations include transmitting voltage pulses corresponding to a subpart of a vector of input data to the crosspoint array. The voltage pulses generate electric currents that are representative of performing multiplication operations at the crosspoint device based on weight values stored at the crosspoint devices. A set of integrators accumulates an electric charge based on the output electric currents from the respective crosspoint devices. The crosspoint array outputs the accumulated charge after iterating for the predetermined number of times. The accumulated charge represents a multiply-add result of the vector of input data and the one or more convolution kernels.
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公开(公告)号：US10423877B2
公开(公告)日：2019-09-24
申请号：US15237459
申请日：2016-08-15
发明人： Charles E. Cox , Harald Huels , Arvind Kumar , Pritish Narayanan , Ahmet S. Ozcan , J. Campbell Scott , Winfried W. Wilcke
摘要： Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.
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6.发明授权公开(公告)号：US12050997B2
公开(公告)日：2024-07-30
申请号：US16884130
申请日：2020-05-27
CPC分类号： G06N3/084 , G11C7/1006 , G11C11/54 , G11C13/0069 , G06N3/063 , G11C2213/77 , G11C2213/79
摘要： A computer implemented method for implementing a convolutional neural network (CNN) using a crosspoint array includes configuring the crosspoint array to implement a convolution layer by storing one or more weights in crosspoint devices of the array. The method further includes making multiple copies of the weights and training the CNN. Training the CNN includes mapping input data of the convolution layer to the crosspoint array in a row-by-row manner. Further the excitation is input in a row-by-row manner into the crosspoint array, thereby creating row-by-row forward output from the crosspoint array. Further, outputs from the crosspoint devices are stored to corresponding integrators. Errors in the outputs as compared to a desired output, from multiple rows are computed and back propagated in a row-by-row manner into the crosspoint array, the computed errors transmitted to a previous convolution layer.
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公开(公告)号：US20230306251A1
公开(公告)日：2023-09-28
申请号：US17701809
申请日：2022-03-23
CPC分类号： G06N3/0635 , G06N3/0481 , G11C13/0061
摘要： A device comprises activation function circuitry configured to implement a non-linear activation function. The activation function circuitry comprises a comparator circuit, a capacitor, and a ramp voltage generator circuit. The capacitor comprises a terminal coupled to a first input terminal of the comparator circuit, and is configured to receive and store an input voltage which corresponds to an input value to the non-linear activation function. The ramp voltage generator circuit is configured to generate a ramp voltage which is applied to a second input terminal of the comparator circuit. The comparator circuit is configured to compare, during a conversion period, the stored input voltage to the ramp voltage, and generate a voltage pulse based on a result of the comparing. The voltage pulse comprises a pulse duration which encodes an activation output value of the non-linear activation function based on the input value to the non-linear activation function.
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公开(公告)号：US20220405554A1
公开(公告)日：2022-12-22
申请号：US17350162
申请日：2021-06-17
IPC分类号： G06N3/063
摘要： Embodiments herein disclose computer-implemented methods, computer program products and computer systems for balancing neural network weight asymmetries. The computer-implemented method may include providing a neural network with weights comprising one or more major conductance pairs and one or more minor conductance pairs. The method may further include programming the one or more major conductance pairs to force an inference output to an expected duration value, determining a positive weight coefficient based on the one or more major conductance pairs and a negative weight coefficient based on the one or more minor conductance pairs, determining one or more target weights based on one or more of the positive weight coefficient and the negative weight coefficient, programming the one or more minor conductance pairs to force the inference output to the expected duration value, and programming the one or more major conductance pairs with the one or more target weights.
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公开(公告)号：US20220392525A1
公开(公告)日：2022-12-08
申请号：US17339046
申请日：2021-06-04
摘要： Embodiments are disclosed for a method. The method includes setting conductances for corresponding non-volatile memory (NVM) devices of a cross-bar array to zero. The method further includes determining a plurality of pulse-widths for the corresponding plurality of NVM devices based on a corresponding plurality of programming errors. Additionally, the method includes programming the NVM devices using the determined pulse-widths. Also, the method includes measuring actual conductances for the corresponding NVM devices. Further, the method includes adjusting scaling factors for the corresponding NVM devices based on the actual conductances and the corresponding programming errors. Additionally, the method includes programming the corresponding NVM devices based on the determined pulse-widths and the scaling factors.
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公开(公告)号：US11514981B1
公开(公告)日：2022-11-29
申请号：US17339046
申请日：2021-06-04
摘要： The method includes setting conductances for corresponding non-volatile memory (NVM) devices of a cross-bar array to zero. The method further includes determining a plurality of pulse-widths for the corresponding plurality of NVM devices based on a corresponding plurality of programming errors. Additionally, the method includes programming the NVM devices using the determined pulse-widths. Also, the method includes measuring actual conductances for the corresponding NVM devices. Further, the method includes adjusting scaling factors for the corresponding NVM devices based on the actual conductances and the corresponding programming errors. Additionally, the method includes programming the corresponding NVM devices based on the determined pulse-widths and the scaling factors.
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