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1.发明申请Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP 有权SMP中服务器节点的无中断，动态热插拔和热删除公开(公告)号：US20040215865A1
公开(公告)日：2004-10-28
申请号：US10424277
申请日：2003-04-28
IPC分类号： G06F013/00
CPC分类号： G06F13/4081
摘要： A data processing system that provides hot-plug add and remove functionality for individual, hot-pluggable components without disrupting current operations of the overall processing system. The processing system includes an interconnect fabric that includes hot plug connector at which an external hot-pluggable component can be coupled to the data processing system and logic components include configuration logic and routing and operating logic. When a hot-pluggable component is connected to the hot plug connector, the service element automatically detects the connection and selects the correct configuration file for the extended system. Once the configuration file is loaded and the system checks of the new element indicates the new element is ready for integration, the new element is integrated into the existing system, and the OS allocates workload to the new element. From a customer perspective, the entire process thus occurs without powering down or disrupting the operation of the existing element.
摘要翻译： 一种数据处理系统，可为单个热插拔组件提供热插拔添加和删除功能，而不会中断整个处理系统的当前操作。 处理系统包括互连结构，其包括热插拔连接器，外部可热插拔组件可以连接到数据处理系统，逻辑组件包括配置逻辑和路由和操作逻辑。 当热插拔组件连接到热插拔连接器时，服务元件会自动检测连接并为扩展系统选择正确的配置文件。 一旦加载了配置文件，并且新元素的系统检查指示新元素可以进行集成，则将新元素集成到现有系统中，并且操作系统将工作负载分配给新元素。 从客户的角度来看，整个过程都是在不掉电或破坏现有元素的操作的情况下进行的。
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2.发明申请公开(公告)号：US20040111547A1
公开(公告)日：2004-06-10
申请号：US10313277
申请日：2002-12-05
IPC分类号： G06F012/00 , G06F012/02 , G06F012/04 , G06F012/08 , G06F012/10 , G06F013/24
CPC分类号： G06F9/4812
摘要： A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the processing system to be dynamically enabled/disabled. When a sequence of instructions constituting a data move operation is being issued, the architected bit is toggled to an interrupt disabled state so that execution of the sequence of instructions occurs without an external interrupt. Following the execution of the sequence of instructions, the architected bit is toggled to an interrupt enabled state, which causes instruction execution to be subjected to external interrupts.
摘要翻译： 提供动态可选择的操作模式的处理器芯片，其中在没有外部中断的情况下执行特定的指令序列。 处理器芯片包括可以由软件设置并且使处理系统的外部中断能够被动态地启用/禁用的架构位。 当正在发出构成数据移动操作的指令序列时，构造的位被切换到中断禁止状态，使得指令序列的执行在没有外部中断的情况下发生。 在执行指令序列之后，构造的位被切换到中断使能状态，这导致指令执行受到外部中断。
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3.发明申请High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system 失效适用于多处理器数据处理系统锁定采集的高速推广机制公开(公告)号：US20040073909A1
公开(公告)日：2004-04-15
申请号：US10268729
申请日：2002-10-10
IPC分类号： G06F009/00
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect. Advantageously, promotion bit fields are handled separately from data, and the communication of promotion bit fields does not entail the movement of data cache lines.
摘要翻译： 多处理器数据处理系统包括耦合到互连的多个处理器和包含至少一个促销位字段的全局推广设备。 第一处理器执行包括负载型指令的高速指令序列，以在除了至少第二处理器之外的全局促进设备中获取促销位字段。 所述请求可以被耦合到互连的所有处理器可见。 响应于负载型指令的执行，第一处理器的寄存器接收指示通过执行负载型指令是否获取了促销位字段的寄存器位字段。 虽然第一处理器保持不属于第二处理器的升级位字段，但允许第二处理器在互连上发起请求。 优选地，促销比特字段与数据分开处理，并且促销比特字段的通信不需要数据高速缓存行的移动。
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4.发明申请Method, apparatus and system that cache promotion information within a processor separate from instructions and data 有权缓存处理器内的促销信息与指令和数据分离的方法，装置和系统公开(公告)号：US20040073760A1
公开(公告)日：2004-04-15
申请号：US10268739
申请日：2002-10-10
IPC分类号： G06F012/00
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0815
摘要： A data processing system includes a global promotion facility and a plurality of processing units coupled by an interconnect. At least one processing unit among the plurality of processing units includes one or more second caches having cache arrays in which instructions and operand data are cached, an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a promotion bit field within the global promotion facility exclusive of at least one other processing unit, and a promotion cache separate from the one or more second caches. In response to acquisition of the promotion bit field by the first processor, the promotion cache of the first processor stores the promotion bit field separately from instructions and operand data.
摘要翻译： 数据处理系统包括全球推广设施和通过互连耦合的多个处理单元。 多个处理单元中的至少一个处理单元包括具有高速缓存阵列的一个或多个第二高速缓冲存储器，其中指令和操作数据被缓存，指令排序单元，执行单元，执行获取指令以获取内部的提升位字段 全球推广设施，不包括至少一个其他处理单元，以及与所述一个或多个第二高速缓存分开的升级缓存。 响应于由第一处理器获取促销位字段，第一处理器的升级缓存存储与指令和操作数数据分开的促销位字段。
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5.发明申请Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction 失效用于通过执行指令获取多个全球推广设施的方法，装置和系统公开(公告)号：US20040073757A1
公开(公告)日：2004-04-15
申请号：US10268744
申请日：2002-10-10
IPC分类号： G06F012/00
CPC分类号： G06F12/084 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/1433 , Y10S707/99938
摘要： A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields. The first processor executes a single acquisition instruction to concurrently acquire a plurality of promotion bit fields exclusive of at least the second processor. In response to execution of the acquisition instruction, the first processor receives an indication of success or failure of the acquisition instruction, wherein the indication indicates success of the acquisition instruction if all of the plurality of promotion bit fields were concurrently acquired by the first processor and indicates failure of the acquisition instruction if fewer than all of the plurality of promotion bit fields were acquired by the first processor.
摘要翻译： 多处理器数据处理系统包括耦合到互连的第一和第二处理器以及包含多个提升位字段的全局推广设备。 第一处理器执行单个采集指令以同时获取排斥至少第二处理器的多个升级位字段。 响应于所述获取指令的执行，所述第一处理器接收所述获取指令的成功或失败的指示，其中如果所述多个提升位字段是由所述第一处理器同时获取的，则所述指示指示所述获取指令的成功，以及 指示如果所述第一处理器获取的所述多个提升位字段中的少于全部，则所述获取指令失败。
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6.发明申请Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction 失效通过执行分支式指令访问全球推广工具的方法，装置和系统公开(公告)号：US20040073734A1
公开(公告)日：2004-04-15
申请号：US10268742
申请日：2002-10-10
IPC分类号： G06F012/00 , G06F012/14
CPC分类号： G06F12/0831 , G06F9/3004 , G06F9/30054 , G06F9/30072 , G06F9/30087
摘要： A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. The first processor initiates execution of a branch-type instruction to request acquisition of a promotion bit field exclusive of at least the second processor. In response to the branch-type instruction, the first processor issues an access request to acquire the promotion bit field. After the accessing request, a register of the first processor receives a register bit indicating whether or not the promotion bit field was successfully acquired by the access request. As a part of executing the branch-type instruction, the first processor selects among a first execution path and a second execution path in response to the register bit.
摘要翻译： 多处理器数据处理系统包括耦合到互连的第一和第二处理器以及包含至少一个促销位字段的全局推广设备。 第一处理器启动分支型指令的执行，以请求获取除了至少第二处理器之外的促销位字段。 响应于分支型指令，第一处理器发出获取促销位字段的访问请求。 在访问请求之后，第一处理器的寄存器接收指示是否通过访问请求成功获取了促销位字段的寄存器位。 作为执行分支型指令的一部分，第一处理器响应于寄存器位在第一执行路径和第二执行路径之中进行选择。
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公开(公告)号：US20040059871A1
公开(公告)日：2004-03-25
申请号：US10216637
申请日：2002-08-08
IPC分类号： G06F012/08 , G06F012/00
CPC分类号： G06F12/0811
摘要： A set of local invalidation buses for a highly scalable shared cache memory hierarchy is disclosed. A symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. In addition, a group of local invalidation buses is connected between all the level one cache memories and the level two cache memory. The imprecisely inclusive level two cache memory includes a tracking means for imprecisely tracking cache line inclusivity of the level one cache memories. Thus, the level two cache memory does not have dedicated inclusivity bits for tracking the cache line inclusivity of each of the associated level one cache memories. The tracking means includes a last_processor_to_store field and a more_than_two_loads field per cache line. When the more_than_two_loads field is asserted, except for a specific cache line in the level one cache memory associated with the processor indicated in the last_processor_to_store field, all cache lines within the level one cache memories that shared identical information with that specific cache line are invalidated via the local invalidation buses connected between all the level one cache memories and the level two cache memory.
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8.发明申请METHOD AND APPARATUS FOR CONCURRENTLY COMMUNICATING WITH MULTIPLE EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICES 有权与多个嵌入式动态随机访问存储器件进行通信的方法和装置公开(公告)号：US20030014606A1
公开(公告)日：2003-01-16
申请号：US09903720
申请日：2001-07-12
发明人： Ravi Kumar Arimilli , James Stephen Fields JR. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
IPC分类号： G06F012/00
CPC分类号： G06F13/28 , G06F13/4243
摘要： An apparatus for providing concurrent communications between multiple memory devices and a processor is disclosed. Each of the memory device includes a driver, a phase/cycle adjust sensing circuit, and a bus alignment communication logic. Each phase/cycle adjust sensing circuit detects an occurrence of a cycle adjustment from a corresponding driver within a memory device. If an occurrence of a cycle adjustment has been detected, the bus alignment communication logic communicates the occurrence of a cycle adjustment to the processor. The bus alignment communication logic also communicates the occurrence of a cycle adjustment to the bus alignment communication logic in the other memory devices. There are multiple receivers within the processor, and each of the receivers is designed to receive data from a respective driver in a memory device. Each of the receivers includes a cycle delay block. The receiver that had received the occurrence of a cycle adjustment informs the other receivers that did not receive the occurrence of a cycle adjustment to use their cycle delay block to delay the incoming data for at least one cycle.
摘要翻译： 公开了一种用于在多个存储器件和处理器之间提供并发通信的装置。 每个存储器件包括驱动器，相位/周期调整感测电路和总线对准通信逻辑。 每个相位/周期调整感测电路检测来自存储器件内相应的驱动器的周期调整的发生。 如果已经检测到循环调整的发生，则总线对准通信逻辑将处理器的循环调整的发生传达给处理器。 总线对准通信逻辑还将循环调整的发生与其他存储器件中的总线对准通信逻辑进行通信。 处理器内有多个接收器，并且每个接收器被设计成从存储器设备中的相应驱动器接收数据。 每个接收器包括循环延迟块。 接收到发生循环调整的接收器通知其他接收机没有接收周期调整的发生，以使用它们的周期延迟块来延迟输入数据至少一个周期。
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公开(公告)号：US20040236891A1
公开(公告)日：2004-11-25
申请号：US10425420
申请日：2003-04-28
IPC分类号： G06F013/36
CPC分类号： G06F15/17337
摘要： A method and system for providing a multiprocessor processor book that is utilized as a building block for a large scale data processing system. Two 4-way multi-chip modules (MCM) are utilized to create the processor book. The first and second MCMs are configured with normal wiring among their respective processors. An additional wiring is provided that links external buses of each chip of the first MCM with buses of a corresponding chip of the second MCM and vice versa. The additional wiring enables each processor of the first MCM substantially direct access to the distributed memory components of the next MCM with no affinity. The processor book is plugged into a processor rack configured to receive multiple processor books that together make up the large scale data processing system.
摘要翻译： 一种用于提供用作大规模数据处理系统的构建块的多处理器处理器书的方法和系统。 利用两个4路多芯片模块（MCM）来创建处理器书。 第一和第二MCM在它们各自的处理器之间配置有正常的接线。 提供了另外的布线，其将第一MCM的每个芯片的外部总线与第二MCM的相应芯片的总线相链接，反之亦然。 附加布线使得第一MCM的每个处理器基本上直接访问下一个MCM的分布式存储器组件，没有亲和力。 处理器手册插入处理器机架，配置为接收多个处理器书籍，这些书籍一起构成大规模数据处理系统。
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10.发明申请Method and data processing system for microprocessor communication in a cluster-based multi-processor network 失效基于群集的多处理器网络中微处理器通信的方法和数据处理系统公开(公告)号：US20040215899A1
公开(公告)日：2004-10-28
申请号：US10424255
申请日：2003-04-28
IPC分类号： G06F012/00
CPC分类号： G06F9/52 , G06F12/0831
摘要： The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data, which is known to be small enough to fit within the unused bits. The address tenure is then broadcasted as a normal address operation and is snooped by all of the processors. The snooping logic is designed to recognize regular/normal address tenures and these modified address tenures and respond to a receipt of a modified address tenure by removing the synchronization data stored therein and updating the corresponding register location of the PCR.
摘要翻译： 重新定义PCR同步操作的地址保留期，以支持在地址保留期内包含同步数据。 地址占有期内的特定字段的位（例如，地址字段）被重新分配给已知足够小以适合未使用位的同步数据。 然后将地址权限作为正常地址操作广播，并被所有处理器窥探。 窥探逻辑被设计为识别常规/正常地址权属和这些修改的地址权属，并且通过去除存储在其中的同步数据并更新PCR的相应寄存器位置来响应修改的地址保有权的接收。
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