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公开(公告)号:US10379776B2
公开(公告)日:2019-08-13
申请号:US15603728
申请日:2017-05-24
发明人: Deanna P. Berger , Michael A. Blake , Ashraf Elsharif , Kenneth D. Klapproth , Pak-kin Mak , Robert J. Sonnelitter, III , Guy G. Tracy
IPC分类号: G06F12/00 , G06F3/06 , G06F12/0893 , G06F12/0842
摘要: An aspect includes interlocking operations in an address-sliced cache system. A computer-implemented method includes determining whether a dynamic memory relocation operation is in process in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is in process, a key operation is serialized to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is not in process, a plurality of key operation requests is allowed to launch across two or more of the slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the slices and pipes at a same time.
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公开(公告)号:US20160224463A1
公开(公告)日:2016-08-04
申请号:US14613800
申请日:2015-02-04
发明人: Michael A. Blake , Garrett M. Drapala , James F. Driftmyer , Deanna P. Berger , Pak-kin Mak , Timothy J. Slegel , Rebecca S. Wisniewski
CPC分类号: G06F12/02 , G06F12/0811 , G06F12/0815 , G06F12/0848 , G06F12/0884 , G06F12/0897 , G06F2212/282 , G06F2212/283
摘要: A multi-boundary address protection range is provided to prevent key operations from interfering with a data move performed by a dynamic memory relocation (DMR) move operation. Any key operation address that is within the move boundary address range gets rejected back to the hypervisor. Further, logic exists across a set of parallel slices to synchronize the DMR move operation as it crosses a protected boundary address range.
摘要翻译: 提供多边界地址保护范围以防止键操作干扰由动态存储器重定位(DMR)移动操作执行的数据移动。 移动边界地址范围内的任何键操作地址将被拒绝回管理程序。 此外,跨越一组并行片段存在逻辑,以在DMR移动操作跨越受保护的边界地址范围时同步DMR移动操作。
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公开(公告)号:US08930628B2
公开(公告)日:2015-01-06
申请号:US13682136
申请日:2012-11-20
发明人: Deanna P. Berger , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
CPC分类号: G06F12/0811 , G06F9/524 , G06F12/0855 , G06F12/0897
摘要: Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.
摘要翻译: 本发明的各种实施例管理分层存储存储器高速缓存结构。 存储请求队列与多个处理核心中的处理核心相关联。 确定至少一个阻塞条件已经在存储请求队列中发生。 响应于发生的阻塞状态,多个非存储请求和与多个处理核心中的剩余处理核心集相关联的一组存储请求被动态阻止访问存储器高速缓存。
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公开(公告)号:US10795824B2
公开(公告)日:2020-10-06
申请号:US16197669
申请日:2018-11-21
IPC分类号: G06F12/0891 , G06F12/084
摘要: Speculative data return in parallel with an exclusive invalidate request. A requesting processor requests data from a shared cache. The data is owned by another processor. Based on the request, an invalidate request is sent to the other processor requesting the other processor to release ownership of the data. Concurrent to the invalidate request being sent to the other processor, the data is speculatively provided to the requesting processor.
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公开(公告)号:US20180121358A1
公开(公告)日:2018-05-03
申请号:US15860283
申请日:2018-01-02
发明人: Ekaterina M. Ambroladze , Deanna P. Berger , Michael F. Fee , Arthur J. O'Neill , Robert J. Sonnelitter, III
IPC分类号: G06F12/0815 , G06F12/084 , G06F15/173 , G06F12/0831 , G06F12/0817
CPC分类号: G06F12/0815 , G06F12/0817 , G06F12/0831 , G06F12/084 , G06F15/173 , G06F2212/1016 , G06F2212/1032 , G06F2212/314 , G06F2212/60 , G06F2212/601 , G06F2212/622
摘要: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration
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公开(公告)号:US20160232099A1
公开(公告)日:2016-08-11
申请号:US14616784
申请日:2015-02-09
发明人: Ekaterina M. Ambroladze , Deanna P. Berger , Garrett M. Drapala , Michael Fee , Pak-kin Mak , Arthur J. O'Neill, JR. , Diana L. Orf
CPC分类号: G06F12/0868 , G06F3/0619 , G06F3/065 , G06F3/0685 , G06F11/10 , G06F11/1446 , G06F12/0802 , G06F12/0804 , G06F12/0808 , G06F12/0888 , G06F12/0891 , G06F12/0897 , G06F2212/1016 , G06F2212/311 , G06F2212/60 , G06F2212/608
摘要: In an approach for backing up designated data located in a cache, data stored within an index of a cache is identified, wherein the data has an associated designation indicating that the data is applicable to be backed up to a higher level memory. It is determined that the data stored to the cache has been updated. A status associated with the data is adjusted, such that the adjusted status indicates that the data stored to the cache has not been changed. A copy of the data is created. The copy of the data is stored to the higher level memory.
摘要翻译: 在用于备份位于高速缓存中的指定数据的方法中,识别存储在高速缓存的索引内的数据,其中数据具有指示该数据可应用于备份到较高级存储器的相关联的指定。 确定存储到高速缓存的数据已被更新。 调整与数据相关联的状态,使得调整状态指示存储到高速缓存的数据未被改变。 创建数据的副本。 数据的副本存储到较高级别的内存。
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公开(公告)号:US20160217076A1
公开(公告)日:2016-07-28
申请号:US14606048
申请日:2015-01-27
IPC分类号: G06F12/08
CPC分类号: G06F12/0831 , G06F2212/1024 , G06F2212/507 , Y02D10/13
摘要: Cache control is provided. A request for ownership of a requested cache line is received from a first processing node. The requested cache line is owned by a second processing node. A coherency message is issued to the second processing node. A shared buffer is caused to store a speculative copy of the requested cache line. Whether a change to the requested cache line occurred is determined. At least one of the requested cache line or the speculative copy is assigned to the first processing node.
摘要翻译: 提供缓存控制。 从第一处理节点接收对所请求的高速缓存行的所有权的请求。 请求的高速缓存行由第二处理节点拥有。 向第二处理节点发出一致性消息。 导致共享缓冲区存储所请求的高速缓存行的推测性副本。 是否确定发生所请求的高速缓存行的更改。 请求的高速缓存行或推测性副本中的至少一个被分配给第一处理节点。
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公开(公告)号:US20180341422A1
公开(公告)日:2018-11-29
申请号:US15603728
申请日:2017-05-24
发明人: Deanna P. Berger , Michael A. Blake , Ashraf Elsharif , Kenneth D. Klapproth , Pak-kin Mak , Robert J. Sonnelitter, III , Guy G. Tracy
IPC分类号: G06F3/06 , G06F12/0893 , G06F12/0842
CPC分类号: G06F12/0842 , G06F12/0893 , G06F2212/62
摘要: An aspect includes interlocking operations in an address-sliced cache system. A computer-implemented method includes determining whether a dynamic memory relocation operation is in process in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is in process, a key operation is serialized to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is not in process, a plurality of key operation requests is allowed to launch across two or more of the slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the slices and pipes at a same time.
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公开(公告)号:US20180107617A1
公开(公告)日:2018-04-19
申请号:US15842920
申请日:2017-12-15
CPC分类号: G06F13/1673 , G06F13/1652 , G06F13/4022 , G06F13/4234
摘要: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.
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公开(公告)号:US09892067B2
公开(公告)日:2018-02-13
申请号:US14608373
申请日:2015-01-29
CPC分类号: G06F13/1673 , G06F13/1652 , G06F13/4022 , G06F13/4234
摘要: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.
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