TWO-DIMENSIONAL ARRAY OF CMOS CONTROL ELEMENTS

    公开(公告)号:US20170322291A1

    公开(公告)日:2017-11-09

    申请号:US15294130

    申请日:2016-10-14

    申请人: InvenSense, Inc.

    IPC分类号: G01S7/521 H01L27/092

    摘要: An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes two semiconductor devices. The plurality of CMOS control elements include a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements including a semiconductor device of a first class and a semiconductor device of a second class, and a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements including a semiconductor device of the first class and a semiconductor device of a third class. The plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.

    ULTRASONIC TRANSDUCER WITH A NON-UNIFORM MEMBRANE

    公开(公告)号:US20170326594A1

    公开(公告)日:2017-11-16

    申请号:US15469383

    申请日:2017-03-24

    申请人: InvenSense, Inc.

    IPC分类号: B06B1/06

    摘要: A Piezoelectric Micromachined Ultrasonic Transducer (PMUT) device includes a substrate, an edge support structure connected to the substrate, and a membrane connected to the edge support structure such that a cavity is defined between the membrane and the substrate, the membrane configured to allow movement at ultrasonic frequencies, the membrane having non-uniform stiffness. The membrane includes a piezoelectric layer, a first electrode and a second electrode coupled to opposing sides of the piezoelectric layer, and a mechanical support layer coupled to one of the first electrode and the second electrode.

    TWO-DIMENSIONAL ARRAY OF CMOS CONTROL ELEMENTS

    公开(公告)号:US20170322292A1

    公开(公告)日:2017-11-09

    申请号:US15294186

    申请日:2016-10-14

    申请人: InvenSense, Inc.

    IPC分类号: G01S7/521 H01L27/092

    摘要: An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes semiconductor devices. The plurality of CMOS control elements each including a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device and an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device. The plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.

    TWO-DIMENSIONAL ARRAY OF CMOS CONTROL ELEMENTS

    公开(公告)号:US20190247887A1

    公开(公告)日:2019-08-15

    申请号:US16395045

    申请日:2019-04-25

    申请人: InvenSense, Inc.

    IPC分类号: B06B1/06 G06K9/00 G06F3/0354

    摘要: An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes two semiconductor devices. The plurality of CMOS control elements include a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements including a semiconductor device of a first class and a semiconductor device of a second class, and a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements including a semiconductor device of the first class and a semiconductor device of a third class. The plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.