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公开(公告)号：US10071906B2
公开(公告)日：2018-09-11
申请号：US15281589
申请日：2016-09-30
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Fariborz Assaderaghi
CPC classification number: B81C1/00246 , B81B7/0025 , B81B7/007 , B81B2207/015 , B81C1/00531 , B81C1/00539 , B81C1/00801 , B81C2201/0132 , B81C2201/0133 , B81C2201/053 , B81C2203/0735
Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
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公开(公告)号：US10508022B2
公开(公告)日：2019-12-17
申请号：US15477193
申请日：2017-04-03
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Martin Lim , Xiang Li , Li-Wen Hung
Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.
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公开(公告)号：US20180346323A1
公开(公告)日：2018-12-06
申请号：US16101353
申请日：2018-08-10
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Fariborz Assaderaghi
Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
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4.发明申请公开(公告)号：US20170022054A1
公开(公告)日：2017-01-26
申请号：US15291599
申请日：2016-10-12
Applicant: INVENSENSE, INC.
Inventor： Julius Ming-Lin Tsai , Michael J. Daneman
CPC classification number: B81B7/007 , B81B3/0029 , B81B2201/032 , B81B2207/012 , B81B2207/07 , B81C1/00182 , B81C1/00269 , B81C1/00301 , B81C2201/013 , B81C2201/019 , B81C2203/0109 , B81C2203/0792
Abstract: A micro-electro-mechanical system device is disclosed. The micro-mechanical system device comprises a first silicon substrate comprising: a handle layer comprising a first surface and a second surface, the second surface comprises a cavity; an insulating layer deposited over the second surface of the handle layer; a device layer having a third surface bonded to the insulating layer and a fourth surface; a piezoelectric layer deposited over the fourth surface of the device layer; a metal conductivity layer disposed over the piezoelectric layer; a bond layer disposed over a portion of the metal conductivity layer; and a stand-off formed on the first silicon substrate; wherein the first silicon substrate is bonded to a second silicon substrate, comprising: a metal electrode configured to form an electrical connection between the metal conductivity layer formed on the first silicon substrate and the second silicon substrate.
Abstract translation: 公开了一种微机电系统装置。 微机械系统装置包括第一硅衬底，其包括：手柄层，包括第一表面和第二表面，所述第二表面包括空腔; 沉积在手柄层的第二表面上的绝缘层; 具有结合到绝缘层的第三表面和第四表面的器件层; 沉积在器件层的第四表面上的压电层; 设置在所述压电层上的金属导电层; 设置在所述金属导电层的一部分上的接合层; 以及在所述第一硅衬底上形成的间隔件; 其中所述第一硅衬底接合到第二硅衬底，包括：金属电极，被配置为在所述第一硅衬底上形成的所述金属传导层与所述第二硅衬底之间形成电连接。
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5.发明申请RELEASE CHEMICAL PROTECTION FOR INTEGRATED COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) AND MICRO-ELECTRO-MECHANICAL (MEMS) DEVICES 审中-公开用于集成的补充金属氧化物半导体（CMOS）和微机电（MEMS）器件的化学保护公开(公告)号：US20170015547A1
公开(公告)日：2017-01-19
申请号：US15281589
申请日：2016-09-30
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Fariborz Assaderaghi
CPC classification number: B81C1/00246 , B81B7/0025 , B81B7/007 , B81B2207/015 , B81C1/00531 , B81C1/00539 , B81C1/00801 , B81C2201/0132 , B81C2201/0133 , B81C2201/053 , B81C2203/0735
Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
Abstract translation: 提供了保护CMOS层免于暴露于释放化学品的系统和方法。 释放化学品用于释放与CMOS晶片集成的微机电（MEMS）器件。 在互补金属氧化物半导体（CMOS）晶片中产生的钝化开口的侧壁暴露了CMOS释放化学品接触时可能损坏的CMOS晶片的电介质层。 在一个方面，为了保护CMOS晶片并防止电介质层的暴露，钝化开口的侧壁可以被抵抗释放化学品的金属阻挡层覆盖。 另外或可选地，可以在CMOS晶片的表面上沉积绝缘阻挡层，以保护钝化层免于暴露于释放化学品。
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Patent Agency Ranking
公开(公告)号：US10683205B2
公开(公告)日：2020-06-16
申请号：US16101353
申请日：2018-08-10
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Fariborz Assaderaghi
Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
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公开(公告)号：US10160635B2
公开(公告)日：2018-12-25
申请号：US15477202
申请日：2017-04-03
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Martin Lim , Xiang Li , Li-Wen Hung
Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.
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公开(公告)号：US20170327370A1
公开(公告)日：2017-11-16
申请号：US15367766
申请日：2016-12-02
Applicant: INVENSENSE, INC.
Inventor： Julius Ming-Lin Tsai , Michael J. Daneman
CPC classification number: B81B7/007 , B81B3/0029 , B81B2201/032 , B81B2207/012 , B81B2207/07 , B81C1/00182 , B81C1/00269 , B81C1/00301 , B81C2201/013 , B81C2201/019 , B81C2203/0109 , B81C2203/0792
Abstract: A micro-electro-mechanical system device is disclosed. The micro-mechanical system device comprises a first silicon substrate comprising: a handle layer comprising a first surface and a second surface, the second surface comprises a cavity; an insulating layer deposited over the second surface of the handle layer; a device layer having a third surface bonded to the insulating layer and a fourth surface; a piezoelectric layer deposited over the fourth surface of the device layer; a metal conductivity layer disposed over the piezoelectric layer; a bond layer disposed over a portion of the metal conductivity layer; and a stand-off formed on the first silicon substrate; wherein the first silicon substrate is bonded to a second silicon substrate, comprising: a metal electrode configured to form an electrical connection between the metal conductivity layer formed on the first silicon substrate and the second silicon substrate.
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9.发明授权Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices 有权释放用于集成的互补金属氧化物半导体（CMOS）和微机电（MEMS）器件的化学保护公开(公告)号：US09487396B2
公开(公告)日：2016-11-08
申请号：US14477451
申请日：2014-09-04
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Fariborz Assaderaghi
CPC classification number: B81C1/00246 , B81B7/0025 , B81B7/007 , B81B2207/015 , B81C1/00531 , B81C1/00539 , B81C1/00801 , B81C2201/0132 , B81C2201/0133 , B81C2201/053 , B81C2203/0735
Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
Abstract translation: 提供了保护CMOS层免于暴露于释放化学品的系统和方法。 释放化学品用于释放与CMOS晶片集成的微机电（MEMS）器件。 在互补金属氧化物半导体（CMOS）晶片中产生的钝化开口的侧壁暴露了CMOS释放化学品接触时可能损坏的CMOS晶片的电介质层。 在一个方面，为了保护CMOS晶片并防止电介质层的暴露，钝化开口的侧壁可以被抵抗释放化学品的金属阻挡层覆盖。 另外或可选地，可以在CMOS晶片的表面上沉积绝缘阻挡层，以保护钝化层免于暴露于释放化学品。
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10.发明申请RELEASE CHEMICAL PROTECTION FOR INTEGRATED COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) AND MICRO-ELECTRO-MECHANICAL (MEMS) DEVICES 有权用于集成的补充金属氧化物半导体（CMOS）和微机电（MEMS）器件的化学保护公开(公告)号：US20160068388A1
公开(公告)日：2016-03-10
申请号：US14477451
申请日：2014-09-04
Applicant: INVENSENSE, INC.
Inventor： Michael J. Daneman , Fariborz Assaderaghi
CPC classification number: B81C1/00246 , B81B7/0025 , B81B7/007 , B81B2207/015 , B81C1/00531 , B81C1/00539 , B81C1/00801 , B81C2201/0132 , B81C2201/0133 , B81C2201/053 , B81C2203/0735
Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
Abstract translation: 提供了保护CMOS层免于暴露于释放化学品的系统和方法。 释放化学品用于释放与CMOS晶片集成的微机电（MEMS）器件。 在互补金属氧化物半导体（CMOS）晶片中产生的钝化开口的侧壁暴露了CMOS释放化学品接触时可能损坏的CMOS晶片的电介质层。 在一个方面，为了保护CMOS晶片并防止电介质层的暴露，钝化开口的侧壁可以被抵抗释放化学品的金属阻挡层覆盖。 另外或可选地，可以在CMOS晶片的表面上沉积绝缘阻挡层，以保护钝化层免于暴露于释放化学品。
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