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    Data control unit capable of correcting boot errors, and corresponding self-correction method
    1.
    发明授权
    Data control unit capable of correcting boot errors, and corresponding self-correction method 有权
    能够修正启动错误的数据控制单元及相应的自校正方法

    公开(公告)号：US07444543B2

    公开(公告)日：2008-10-28

    申请号：US11149948

    申请日：2005-06-09

    申请人： Irene Babudri ,  Marco Roveda ,  Rino Micheloni

    发明人： Irene Babudri ,  Marco Roveda ,  Rino Micheloni

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1417 ,  G06F11/076

    摘要： A boot method for a data control unit downloads boot information from a nonvolatile memory into a temporary buffer of a boot-activation unit. A processing unit is activated by the boot-activation unit; a boot code is executed by the processing unit; and an operating code is downloaded from the nonvolatile memory into a volatile memory through the boot-activation unit. To correct possible errors in the block of the nonvolatile memory containing information and boot codes, the boot-activation unit verifies whether the boot information downloaded into its volatile memory has a critical-error condition and activates a spare memory portion of the nonvolatile memory in presence of the critical-error condition.

    摘要翻译： 用于数据控制单元的引导方法将引导信息从非易失性存储器下载到引导启动单元的临时缓冲器中。 处理单元由启动激活单元激活; 由处理单元执行引导代码; 并且通过引导启动单元将操作代码从非易失性存储器下载到易失性存储器中。 为了纠正包含信息和引导代码的非易失性存储器的块中的可能错误，引导激活单元验证下载到其易失性存储器中的引导信息是否具有关键错误状况，并在存在时激活非易失性存储器的备用存储器部分 的关键错误条件。

    Data control unit capable of correcting boot errors, and corresponding self-correction method
    2.
    发明申请
    Data control unit capable of correcting boot errors, and corresponding self-correction method 有权
    能够修正启动错误的数据控制单元及相应的自校正方法

    公开(公告)号：US20060062046A1

    公开(公告)日：2006-03-23

    申请号：US11149948

    申请日：2005-06-09

    申请人： Irene Babudri ,  Marco Roveda ,  Rino Micheloni

    发明人： Irene Babudri ,  Marco Roveda ,  Rino Micheloni

    IPC分类号： G11C16/06

    CPC分类号： G06F11/1417 ,  G06F11/076

    摘要： A boot method for a data control unit downloads boot information from a nonvolatile memory into a temporary buffer of a boot-activation unit. A processing unit is activated by the boot-activation unit; a boot code is executed by the processing unit; and an operating code is downloaded from the nonvolatile memory into a volatile memory through the boot-activation unit. To correct possible errors in the block of the nonvolatile memory containing information and boot codes, the boot-activation unit verifies whether the boot information downloaded into its volatile memory has a critical-error condition and activates a spare memory portion of the nonvolatile memory in presence of the critical-error condition.

    摘要翻译： 用于数据控制单元的引导方法将引导信息从非易失性存储器下载到引导启动单元的临时缓冲器中。 处理单元由启动激活单元激活; 由处理单元执行引导代码; 并且通过引导启动单元将操作代码从非易失性存储器下载到易失性存储器中。 为了纠正包含信息和引导代码的非易失性存储器的块中的可能错误，引导激活单元验证下载到其易失性存储器中的引导信息是否具有关键错误状况，并在存在时激活非易失性存储器的备用存储器部分 的关键错误条件。

    Embedded storage device with integrated data-management functions and storage system incorporating it
    4.
    发明申请
    Embedded storage device with integrated data-management functions and storage system incorporating it 审中-公开
    具有集成数据管理功能的嵌入式存储设备和并入其中的存储系统

    公开(公告)号：US20060053252A1

    公开(公告)日：2006-03-09

    申请号：US11205766

    申请日：2005-08-16

    申请人： Stefano Ghezzi ,  Marco Roveda ,  Stefano Saltutti ,  Giorgio Scarioni

    发明人： Stefano Ghezzi ,  Marco Roveda ,  Stefano Saltutti ,  Giorgio Scarioni

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0664 ,  G06F3/0679

    摘要： In a storage system, a system controller is connected to an embedded storage device for supervising writing and reading operations in the embedded storage device. A data manager based upon a microprocessor is integrated in the embedded storage device and provides a high-level abstraction of the physical organization of the embedded storage device through the definition of an own logic map. The data manager is implemented outside the controller. The controller is formed in a first semiconductor material region, the embedded storage device is formed in a second semiconductor material region distinct from the first semiconductor material region, and the data manager is formed in a third semiconductor material region distinct from the first semiconductor material region.

    摘要翻译： 在存储系统中，系统控制器连接到嵌入式存储设备，用于监控嵌入式存储设备中的写入和读取操作。 基于微处理器的数据管理器集成在嵌入式存储设备中，并且通过定义自己的逻辑图来提供嵌入式存储设备的物理组织的高级抽象。 数据管理器在控制器外部实现。 控制器形成在第一半导体材料区域中，嵌入式存储装置形成在与第一半导体材料区域不同的第二半导体材料区域中，数据管理器形成在与第一半导体材料区域不同的第三半导体材料区域中 。

    Method of managing fails in a non-volatile memory device and relative memory device
    5.
    发明授权
    Method of managing fails in a non-volatile memory device and relative memory device 有权
    在非易失性存储器件和相对存储器件中管理失败的方法

    公开(公告)号：US07571362B2

    公开(公告)日：2009-08-04

    申请号：US11557786

    申请日：2006-11-08

    申请人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

    发明人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

    IPC分类号： G01C29/00

    CPC分类号： G11C29/76 ,  G11C29/006 ,  G11C2029/1208

    摘要： A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

    摘要翻译： 在包括分组在数据存储单元块中的单元阵列的非易失性存储器件中的管理失败的方法包括在阵列中定义用户可寻址的单元块的第一子集以及单元的冗余块的第二子集。 在阵列中定义了非用户可寻址单元块的第三子集，用于存储第三子块的块的可寻址寻址页的各个代码的坏块地址表。 第三子集的每一页与相应的冗余块相关联。 如果在存储器件的工作寿命期间，在测试阶段中先前判断良好的一个单元的块变得失败，则每个块被标记为坏，并且随机存取存储器中存储的表被更新。

    MEMORY ARCHITECTURE WITH SERIAL PERIPHERAL INTERFACE
    6.
    发明申请
    MEMORY ARCHITECTURE WITH SERIAL PERIPHERAL INTERFACE 有权
    具有串行外围接口的存储器架构

    公开(公告)号：US20070115743A1

    公开(公告)日：2007-05-24

    申请号：US11530199

    申请日：2006-09-08

    申请人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

    发明人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

    IPC分类号： G11C7/00

    CPC分类号： G06F13/4282 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C2216/30

    摘要： A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

    摘要翻译： 存储器架构包括包括命令集的存储器和用于将存储器连接到通用主机设备的串行外设接口（SPI）。 SPI包括用于从主机设备向存储器的输入提供输出数据的数据; 用于将输出数据从存储器提供给主机设备的输入的数据输出线; 由主机设备驱动的时钟线; 以及允许主机设备打开和关闭存储器的启用行。 内存是一个NAND闪存。 SPI包括一个I / O寄存器块，包括一个SPI标签寄存器和一个数据寄存器，用于分别从相应的SPI标签寄存器驱动指向存储器的数据，命令和地址。

    Memory architecture with serial peripheral interface
    7.
    发明授权
    Memory architecture with serial peripheral interface 有权
    具有串行外设接口的内存架构

    公开(公告)号：US07793031B2

    公开(公告)日：2010-09-07

    申请号：US11530199

    申请日：2006-09-08

    申请人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Maurizio Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

    发明人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Maurizio Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

    IPC分类号： G06F13/20 ,  G06F13/38 ,  G06F13/00

    CPC分类号： G06F13/4282 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C2216/30

    摘要： A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

    摘要翻译： 存储器架构包括包括命令集的存储器和用于将存储器连接到通用主机设备的串行外设接口（SPI）。 SPI包括用于从主机设备向存储器的输入提供输出数据的数据; 用于将输出数据从存储器提供给主机设备的输入的数据输出线; 由主机设备驱动的时钟线; 以及允许主机设备打开和关闭存储器的启用行。 内存是一个NAND闪存。 SPI包括一个I / O寄存器块，包括一个SPI标签寄存器和一个数据寄存器，用于分别从相应的SPI标签寄存器驱动指向存储器的数据，命令和地址。

    METHOD OF MANAGING FAILS IN A NON-VOLATILE MEMORY DEVICE AND RELATIVE MEMORY DEVICE
    9.
    发明申请
    METHOD OF MANAGING FAILS IN A NON-VOLATILE MEMORY DEVICE AND RELATIVE MEMORY DEVICE 有权
    在非易失性存储器件和相对存储器件中管理故障的方法

    公开(公告)号：US20070109856A1

    公开(公告)日：2007-05-17

    申请号：US11557786

    申请日：2006-11-08

    申请人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

    发明人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

    IPC分类号： G11C16/06

    CPC分类号： G11C29/76 ,  G11C29/006 ,  G11C2029/1208

    摘要： A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

    摘要翻译： 在包括分组在数据存储单元块中的单元阵列的非易失性存储器件中的管理失败的方法包括在阵列中定义用户可寻址的单元块的第一子集以及单元的冗余块的第二子集。 在非易失性存储器件的晶片上的测试期间，包括第一子集中的至少一个故障单元的每个块被定位。 每个块被标记为坏，并且各个代码的坏块地址表存储在非易失性存储器缓冲器中。 在上电时，坏块地址表从非易失性存储器缓冲区复制到随机存取存储器。 通过查找坏块地址表来验证第一子集的存储器单元的块是坏的，并且如果块是坏的，则重新映射对相应的冗余单元块的访问。 在阵列中定义了非用户可寻址单元块的第三子集，用于存储第三子块的块的可寻址寻址页的各个代码的坏块地址表。 第三子集的每一页与相应的冗余块相关联。 如果在存储器件的工作寿命期间，在测试阶段中先前判断良好的一个单元的块变得失败，则每个块被标记为坏，并且随机存取存储器中存储的表被更新。