公开(公告)号：US07793031B2

公开(公告)日：2010-09-07

申请号：US11530199

申请日：2006-09-08

申请人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Maurizio Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

发明人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Maurizio Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

IPC分类号： G06F13/20 ,  G06F13/38 ,  G06F13/00

CPC分类号： G06F13/4282 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C2216/30

摘要： A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

摘要翻译： 存储器架构包括包括命令集的存储器和用于将存储器连接到通用主机设备的串行外设接口（SPI）。 SPI包括用于从主机设备向存储器的输入提供输出数据的数据; 用于将输出数据从存储器提供给主机设备的输入的数据输出线; 由主机设备驱动的时钟线; 以及允许主机设备打开和关闭存储器的启用行。 内存是一个NAND闪存。 SPI包括一个I / O寄存器块，包括一个SPI标签寄存器和一个数据寄存器，用于分别从相应的SPI标签寄存器驱动指向存储器的数据，命令和地址。

公开(公告)号：US20070109856A1

公开(公告)日：2007-05-17

申请号：US11557786

申请日：2006-11-08

申请人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

发明人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

IPC分类号： G11C16/06

CPC分类号： G11C29/76 ,  G11C29/006 ,  G11C2029/1208

摘要： A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

摘要翻译： 在包括分组在数据存储单元块中的单元阵列的非易失性存储器件中的管理失败的方法包括在阵列中定义用户可寻址的单元块的第一子集以及单元的冗余块的第二子集。 在非易失性存储器件的晶片上的测试期间，包括第一子集中的至少一个故障单元的每个块被定位。 每个块被标记为坏，并且各个代码的坏块地址表存储在非易失性存储器缓冲器中。 在上电时，坏块地址表从非易失性存储器缓冲区复制到随机存取存储器。 通过查找坏块地址表来验证第一子集的存储器单元的块是坏的，并且如果块是坏的，则重新映射对相应的冗余单元块的访问。 在阵列中定义了非用户可寻址单元块的第三子集，用于存储第三子块的块的可寻址寻址页的各个代码的坏块地址表。 第三子集的每一页与相应的冗余块相关联。 如果在存储器件的工作寿命期间，在测试阶段中先前判断良好的一个单元的块变得失败，则每个块被标记为坏，并且随机存取存储器中存储的表被更新。

公开(公告)号：US08582364B2

公开(公告)日：2013-11-12

申请号：US13155347

申请日：2011-06-07

申请人： Marco Maccarrone ,  Giuseppe Giannini ,  Demetrio Pellicone

发明人： Marco Maccarrone ,  Giuseppe Giannini ,  Demetrio Pellicone

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G06F1/28 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G06F12/0802 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2213/0032 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

公开(公告)号：US20110235411A1

公开(公告)日：2011-09-29

申请号：US13155347

申请日：2011-06-07

申请人： Marco Maccarrone ,  Giuseppe Giannini ,  Demetrio Pellicone

发明人： Marco Maccarrone ,  Giuseppe Giannini ,  Demetrio Pellicone

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G06F1/28 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G06F12/0802 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2213/0032 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

摘要翻译： 在包括存储器单元矩阵的存储器件的实施例中，其中存储器单元布置在多个存储器单元串中，每个存储单元串包括至少两个串联的存储器单元，至少两个存储器单元串的组被连接到 并且其中所述存储器单元适于被编程为至少第一编程状态和第二编程状态，存储数据的方法包括利用用于写入数据的每个存储器单元串的单个存储器单元， 其中所述利用包括使单个存储器单元进入第二编程状态，所述串的剩余存储单元保持在第一编程状态。

公开(公告)号：US20100039858A1

公开(公告)日：2010-02-18

申请号：US12123359

申请日：2008-05-19

申请人： Marco MACCARRONE ,  Giuseppe GIANNINI ,  Demetrio PELLICONE

发明人： Marco MACCARRONE ,  Giuseppe GIANNINI ,  Demetrio PELLICONE

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G06F1/28 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G06F12/0802 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2213/0032 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

摘要翻译： 在包括存储器单元矩阵的存储器件的实施例中，其中存储器单元布置在多个存储器单元串中，每个存储单元串包括至少两个串联的存储器单元，至少两个存储器单元串的组被连接到 并且其中所述存储器单元适于被编程为至少第一编程状态和第二编程状态，存储数据的方法包括利用用于写入数据的每个存储器单元串的单个存储器单元， 其中所述利用包括使单个存储器单元进入第二编程状态，所述串的剩余存储单元保持在第一编程状态。

公开(公告)号：US20070115743A1

公开(公告)日：2007-05-24

申请号：US11530199

申请日：2006-09-08

申请人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

发明人： Laura Sartori ,  Adamo Corsi ,  Marco Roveda ,  Giuseppe Lorusso ,  Daniela Ruggeri ,  Demetrio Pellicone

IPC分类号： G11C7/00

CPC分类号： G06F13/4282 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C2216/30

摘要： A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

摘要翻译： 存储器架构包括包括命令集的存储器和用于将存储器连接到通用主机设备的串行外设接口（SPI）。 SPI包括用于从主机设备向存储器的输入提供输出数据的数据; 用于将输出数据从存储器提供给主机设备的输入的数据输出线; 由主机设备驱动的时钟线; 以及允许主机设备打开和关闭存储器的启用行。 内存是一个NAND闪存。 SPI包括一个I / O寄存器块，包括一个SPI标签寄存器和一个数据寄存器，用于分别从相应的SPI标签寄存器驱动指向存储器的数据，命令和地址。

公开(公告)号：US08018771B2

公开(公告)日：2011-09-13

申请号：US12123359

申请日：2008-05-19

申请人： Marco Maccarrone ,  Giuseppe Giannini ,  Demetrio Pellicone

发明人： Marco Maccarrone ,  Giuseppe Giannini ,  Demetrio Pellicone

IPC分类号： G11C365/04

CPC分类号： G11C16/10 ,  G06F1/28 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G06F12/0802 ,  G06F13/4282 ,  G06F2212/222 ,  G06F2213/0032 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

摘要翻译： 在包括存储器单元矩阵的存储器件的实施例中，其中存储器单元布置在多个存储器单元串中，每个存储单元串包括至少两个串联的存储器单元，至少两个存储器单元串的组被连接到 并且其中所述存储器单元适于被编程为至少第一编程状态和第二编程状态，存储数据的方法包括利用用于写入数据的每个存储器单元串的单个存储器单元， 其中所述利用包括使单个存储器单元进入第二编程状态，所述串的剩余存储单元保持在第一编程状态。

公开(公告)号：US07571362B2

公开(公告)日：2009-08-04

申请号：US11557786

申请日：2006-11-08

申请人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

发明人： Demetrio Pellicone ,  Adamo Corsi ,  Marco Roveda ,  Concetta Di Tuoro ,  Procolo Carannante ,  Gianfranco Ferrante

IPC分类号： G01C29/00

CPC分类号： G11C29/76 ,  G11C29/006 ,  G11C2029/1208

摘要： A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

摘要翻译： 在包括分组在数据存储单元块中的单元阵列的非易失性存储器件中的管理失败的方法包括在阵列中定义用户可寻址的单元块的第一子集以及单元的冗余块的第二子集。 在阵列中定义了非用户可寻址单元块的第三子集，用于存储第三子块的块的可寻址寻址页的各个代码的坏块地址表。 第三子集的每一页与相应的冗余块相关联。 如果在存储器件的工作寿命期间，在测试阶段中先前判断良好的一个单元的块变得失败，则每个块被标记为坏，并且随机存取存储器中存储的表被更新。