公开(公告)号：US5789795A

公开(公告)日：1998-08-04

申请号：US579824

申请日：1995-12-28

申请人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

发明人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

摘要翻译： 具有形成在半导体衬底上的半导体衬底和抗熔丝结构的集成电路。 反熔丝结构包括金属一层和设置在金属一层上方的抗熔丝层。 当抗熔丝结构未被编程时，抗熔丝层具有第一电阻值，并且当编程防熔丝结构时，抗熔丝层具有低于第一电阻值的第二电阻值。 还提供了设置在反熔丝层上方的蚀刻停止层，并且设置在蚀刻停止层上方的金属间氧化物层与金属间氧化物层在其中形成通孔。 此外，还提供了设置在金属间氧化物层上方的金属二层。 在该结构中，金属二层的一部分通过金属间氧化物层中的通孔与抗熔融层电接触。

公开(公告)号：US6156588A

公开(公告)日：2000-12-05

申请号：US102367

申请日：1998-06-23

申请人： Ivan Sanchez ,  Miguel A. Delgado

发明人： Ivan Sanchez ,  Miguel A. Delgado

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.

摘要翻译： 本发明一般涉及集成电路，尤其涉及在集成电路制造期间形成抗熔丝结构的方法。 在本发明的示例性实施例中，在半导体衬底上形成导电基层。 在导电基底层上形成绝缘层，并将其图形化以暴露导电基底层的一部分。 在绝缘层和导电性基底层的露出部分上形成反熔丝层。 在反熔丝层上形成导电保护层。 通过依次去除导电保护层的一部分以及反熔丝层和绝缘层的下面部分，形成反熔丝岛。 在形成抗熔丝岛之后，导电基底层被图案化。 本发明提供了形成与亚微米器件几何相容的抗熔丝结构的简化方法。

公开(公告)号：US5686171A

公开(公告)日：1997-11-11

申请号：US176353

申请日：1993-12-30

申请人： Edward R. Vokoun ,  Miguel A. Delgado ,  Gregory N. Carter ,  Brian D. Richardson ,  Rajive Dhar ,  Elizabeth A. Chambers

发明人： Edward R. Vokoun ,  Miguel A. Delgado ,  Gregory N. Carter ,  Brian D. Richardson ,  Rajive Dhar ,  Elizabeth A. Chambers

IPC分类号： B81C1/00 ,  H01L21/301 ,  H01L21/78 ,  B32B9/00

CPC分类号： H01L21/78 ,  B81C1/00873 ,  Y10S428/901 ,  Y10S438/975 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

摘要翻译： 一种在半导体晶片上形成划线的方法，包括以下步骤：（a）提供半导体衬底; 和（b）在交替的导电和绝缘类型的半导体衬底上依次提供多个层，其中每个层设置有相对于期望的划线位置的细长的开口，并且其中至少一些 多个层的宽度大于先前层的开口，使得完成的划线的至少一个侧壁具有从其底部向外延伸的明显斜率。 因此，本发明的结构是具有倾斜侧壁的划线，其大大减少了划线污染问题，并且在随后的旋涂过程中增强了平面化。 划线可以是层中的细长开口，也可以是在层中形成的细长台面。

公开(公告)号：US5943591A

公开(公告)日：1999-08-24

申请号：US890910

申请日：1997-07-10

申请人： Edward R. Vokoun ,  Miguel A. Delgado ,  Gregory N. Carter ,  Brian D. Richardson ,  Rajive Dhar ,  Elizabeth A. Chambers

发明人： Edward R. Vokoun ,  Miguel A. Delgado ,  Gregory N. Carter ,  Brian D. Richardson ,  Rajive Dhar ,  Elizabeth A. Chambers

IPC分类号： B81C1/00 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L21/78 ,  B81C1/00873 ,  Y10S428/901 ,  Y10S438/975 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

摘要翻译： 一种在半导体晶片上形成划线的方法，包括以下步骤：（a）提供半导体衬底; 和（b）在交替的导电和绝缘类型的半导体衬底上依次提供多个层，其中每个层设置有相对于期望的划线位置的细长的开口，并且其中至少一些 多个层的宽度大于先前层的开口，使得完成的划线的至少一个侧壁具有从其底部向外延伸的明显斜率。 因此，本发明的结构是具有倾斜侧壁的划线，其大大减少了划线污染问题，并且在随后的旋涂过程中增强了平面化。 划线可以是层中的细长开口，也可以是在层中形成的细长台面。

公开(公告)号：US5391513A

公开(公告)日：1995-02-21

申请号：US171590

申请日：1993-12-22

申请人： Miguel A. Delgado ,  Stacy W. Hall

发明人： Miguel A. Delgado ,  Stacy W. Hall

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An improved method for forming vias in an anti-fuse semiconductor device through an oxide layer to an underlying metallic layer. A wet etch is performed on the oxide layer at selected regions where vias are to be formed. The wet etch is controlled such that a first recessed area is formed in the oxide layer at the selected regions. The first recessed area formed by the wet etch extends only partially through the oxide layer towards the underlying metallic layer. Additionally, the first recessed area is formed having a smoothly shaped contour. Next, a dry etch is performed on the oxide layer at the selected regions where the vias are to be formed. The dry etch is performed within the first recessed area. The second recessed area has a smaller cross sectional area than the first recessed area such that the second recessed area is peripherally bordered by the first recessed area. The second recessed area extends from the bottom of the first recessed area completely through the remaining oxide layer to the underlying metallic layer. In so doing, when amorphous silicon is deposited into the vias, cusping of the amorphous silicon within the vias is substantially reduced. As a result, the step of depositing a spacer oxide to fill in notches created by cusping of the amorphous silicon layer is eliminated. Consequently, when the amorphous silicon is removed or etched from selected strap vias, because no spacer oxide has been deposited, no deleterious residue or "dog ears" of amorphous silicon remain within the strap vias.

摘要翻译： 一种用于在抗熔丝半导体器件中通过氧化物层到底层金属层形成通孔的改进方法。 在要形成通孔的选定区域处对氧化物层进行湿蚀刻。 控制湿蚀刻使得在选定区域的氧化物层中形成第一凹陷区域。 通过湿蚀刻形成的第一凹陷区域仅部分地延伸穿过氧化物层朝向下面的金属层。 此外，第一凹陷区域形成为具有平滑形状的轮廓。 接下来，在要形成通孔的选定区域处对氧化物层进行干蚀刻。 干蚀刻在第一凹陷区域内执行。 第二凹陷区域具有比第一凹陷区域更小的横截面积，使得第二凹陷区域由第一凹陷区域周边地界定。 第二凹陷区域从第一凹陷区域的底部完全延伸穿过剩余的氧化物层到下面的金属层。 这样做时，当非晶硅沉积到通孔中时，通孔内的非晶硅的通孔显着减少。 结果，消除了填充由非晶硅层的沟槽产生的凹口的间隔氧化物的沉积步骤。 因此，当从选定的带通孔去除或蚀刻非晶硅时，由于没有沉积间隔氧化物，所以非织物硅中的有害残留物或“狗耳”不存在于带通孔内。

公开(公告)号：US5795815A

公开(公告)日：1998-08-18

申请号：US699492

申请日：1996-08-19

申请人： Edward R. Vokoun ,  Miguel A. Delgado ,  Gregory N. Carter ,  Brian D. Richardson ,  Rajive Dhar ,  Elizabeth A. Chambers

发明人： Edward R. Vokoun ,  Miguel A. Delgado ,  Gregory N. Carter ,  Brian D. Richardson ,  Rajive Dhar ,  Elizabeth A. Chambers

IPC分类号： B81C1/00 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L21/78 ,  B81C1/00873 ,  Y10S428/901 ,  Y10S438/975 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

公开(公告)号：US5387311A

公开(公告)日：1995-02-07

申请号：US17542

申请日：1993-02-16

申请人： Stacy W. Hall ,  Miguel A. Delgado

发明人： Stacy W. Hall ,  Miguel A. Delgado

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/306

CPC分类号： H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002 ,  Y10S148/055

摘要： A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.

摘要翻译： 一种用于去除反熔丝结构的连接通孔和开口区域中的多余间隔物的方法，而不会通过过蚀刻而使过孔中的抗熔丝层变薄。 在反熔丝结构中，间隔层沉积在反熔丝层上，其中结构中的通孔使较薄的间隔物层沉积在通孔中。 实现间隔层的第一蚀刻，以在通孔中提供保护隔离物。 蚀刻完全去除了通孔中的间隔物之间​​的间隔物材料的较薄部分而没有过蚀刻，而一些隔离材料部分保留在反熔丝结构的另一个开放区域上。 指定的保险丝通孔被掩蔽，并且完成剩余间隔物材料的第二次蚀刻。 该方法从连接通孔和保险丝通孔周围的其他区域去除多余的间隔物材料，并且防止熔丝通孔中的抗熔丝层从过蚀刻过程变薄。