公开(公告)号：US5789795A

公开(公告)日：1998-08-04

申请号：US579824

申请日：1995-12-28

申请人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

发明人： Ivan Sanchez ,  Yu-Pin Han ,  Miguel A. Delgado ,  Ying-Tsong Loh

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

摘要翻译： 具有形成在半导体衬底上的半导体衬底和抗熔丝结构的集成电路。 反熔丝结构包括金属一层和设置在金属一层上方的抗熔丝层。 当抗熔丝结构未被编程时，抗熔丝层具有第一电阻值，并且当编程防熔丝结构时，抗熔丝层具有低于第一电阻值的第二电阻值。 还提供了设置在反熔丝层上方的蚀刻停止层，并且设置在蚀刻停止层上方的金属间氧化物层与金属间氧化物层在其中形成通孔。 此外，还提供了设置在金属间氧化物层上方的金属二层。 在该结构中，金属二层的一部分通过金属间氧化物层中的通孔与抗熔融层电接触。

公开(公告)号：US5753540A

公开(公告)日：1998-05-19

申请号：US699867

申请日：1996-08-20

申请人： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

发明人： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

摘要翻译： 公开了一种用于编程反熔丝结构的方法。 反熔丝结构通过在底部和顶部电极之间施加具有交流电脉冲的交流电来编程，以产生穿过夹在电极之间的反熔丝的导电路径。 由于由于每个交流脉冲而产生的电子流，传导路径增量地形成，从而在反熔丝材料的基本中心部分处限定导电路径。

公开(公告)号：US5783467A

公开(公告)日：1998-07-21

申请号：US582844

申请日：1995-12-29

申请人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

发明人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/82

CPC分类号： H01L27/11206 ,  H01L27/112

摘要： An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

摘要翻译： 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5793094A

公开(公告)日：1998-08-11

申请号：US579780

申请日：1995-12-28

申请人： Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

发明人： Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh ,  Walter D. Parmantie

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

摘要翻译： 一种用于基本上减少在集成电路晶片上形成的抗熔丝结构的编程电压的变化的方法。 反熔丝结构具有金属一层，设置在金属一层上方的抗熔丝层，设置在抗熔融层上方的氧化物层，以及氧化物层中的通孔到反熔丝 用于接收金属二材料的沉积的层。 该方法包括以下步骤：当编程时，通过降低所选择的反熔丝区域与金属层和金属二层中的一个的原子的扩散，使选择的抗熔丝区域易于熔融链接形成 在金属一层和金属两层之间施加电压。 所选择的反熔丝区域位于反熔丝层中，并且基本上邻近通孔正下方的反熔丝区域的外部。 该方法还包括将金属二材料沉积到通孔中的步骤。

公开(公告)号：US5821558A

公开(公告)日：1998-10-13

申请号：US792791

申请日：1997-02-03

申请人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

发明人： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/04 ,  H01L27/02

CPC分类号： H01L27/11206 ,  H01L27/112

摘要： An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

摘要翻译： 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5793640A

公开(公告)日：1998-08-11

申请号：US773171

申请日：1996-12-26

申请人： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

发明人： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC分类号： G01R27/26 ,  G01R27/00

CPC分类号： G01R27/2605

摘要： A computer-aided method and system are provided for obtaining a measurement of the capacitance value of a device under test (DUT). The complex impedance of a device under test (DUT) is measured at two nearby frequencies using an RLC meter. The two complex impedance values are then stored in a computer readable medium. The DUT is modeled by a programmed computer as a four element RLC model circuit including a resistor and inductor in series with a parallel RC circuit having a single capacitor which represents the capacitance of the DUT. Four equations which describe the electrical characteristics of the four element RLC model circuit are stored in a computer readable medium. The four measured values of complex impedance are substituted by the computer into the four stored equations. Values are obtained for the four individual RLC circuit elements by solving the four equations. The four unknown values are obtained by use of an optimization routine and then stored to a computer readable medium. The value capacitor element representing the capacitance of the DUT is then displayed.

摘要翻译： 提供了一种计算机辅助方法和系统，用于获得待测器件（DUT）的电容值的测量。 被测设备（DUT）的复阻抗使用RLC仪在两个附近的频率下测量。 然后将两个复阻抗值存储在计算机可读介质中。 DUT被编程的计算机建模为四元件RLC模型电路，其包括与表示DUT的电容的单个电容器的并联RC电路串联的电阻器和电感器。 描述四元素RLC模型电路的电特性的四个等式被存储在计算机可读介质中。 复阻抗的四个测量值被计算机代入四个存储的方程。 通过求解四个等式获得四个单独的RLC电路元件的值。 通过使用优化例程获得四个未知值，然后将其存储到计算机可读介质中。 然后显示表示DUT的电容的值电容器元件。

公开(公告)号：US5773317A

公开(公告)日：1998-06-30

申请号：US572944

申请日：1995-12-15

申请人： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

发明人： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： The use of a test chip having a wide channel MOSFETs of different channel widths and effective gate lengths allows for an experimental determination of the fringe capacitance per unit width. The use of channel widths greater than 100 microns increases the accuracy of the measured capacitance values.

摘要翻译： 使用具有不同沟道宽度和有效栅极长度的宽沟道MOSFET的测试芯片允许对每单位宽度的边缘电容进行实验测定。 使用大于100微米的通道宽度会增加测量电容值的精度。

公开(公告)号：US6007641A

公开(公告)日：1999-12-28

申请号：US818228

申请日：1997-03-14

申请人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

发明人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/316 ,  H01L29/51 ,  B08B3/00

CPC分类号： H01L21/28202 ,  H01L21/02063 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02307 ,  H01L21/31612 ,  H01L21/31662 ,  H01L29/518

摘要： In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

摘要翻译： 在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。 首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。 第二，水性漂洗去除氧化的有机物质和金属污染物。 第三，将集成电路浸在氟化氢和硝酸的水溶液中。 氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。 所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。 干燥步骤从集成电路中去除冲洗水。 最后，氧化物形成步骤提供相对纯的氧化物层。 在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。 在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。 本发明的主要优点是由于硝酸而改善的钙去除。

公开(公告)号：US4868138A

公开(公告)日：1989-09-19

申请号：US172299

申请日：1988-03-23

申请人： Tsiu C. Chan ,  Yu-Pin Han

发明人： Tsiu C. Chan ,  Yu-Pin Han

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/6659

摘要： A process for forming electrical interconnect on MOS semiconductor integrated circuits includes the formation of a capping layer of oxide over the first level poly layer prior to patterning. The capping layer is then removed over selected regions. The conductive layer and capping oxide layer are then patterned to form transistor gates and interconnect. Source/drain regions are formed in active areas of the integrated circuit, and sidewall oxide is formed next to the patterned gate regions. When a second layer of interconnect is formed and patterned over the integrated circuit, contact between the first and second interconnect layers is made in the previously defined selected regions.

公开(公告)号：US06429144B1

公开(公告)日：2002-08-06

申请号：US09473451

申请日：1999-12-28

申请人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

发明人： Landon B. Vines ,  Felix H. Fujishiro ,  Yu-Pin Han

IPC分类号： H01L21302

CPC分类号： H01L21/31111 ,  H01L21/0206 ,  H01L21/28211 ,  H01L21/28238

摘要： In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer. In the case of a gate oxide, the method removes a sacrificial oxide in preparation for gate oxide growth. In the case of formation of the submetal dielectric, oxide formation involves an TEOS oxide deposition. A key advantage of the invention is the improved calcium removal due to the nitric acid.

摘要翻译： 在集成电路的制造中，使用以下步骤用相对纯的氧化物代替污染的氧化物。 首先，将部分制造的集成电路沐浴在过氧化氢和氢氧化铵的水溶液中以氧化有机材料并减弱金属污染物与集成电路基板的接合。 第二，水性漂洗去除氧化的有机物质和金属污染物。 第三，将集成电路浸在氟化氢和硝酸的水溶液中。 氢氟酸蚀刻污染的氧化物; 硝酸与钙和金属污染物结合，氧化物被蚀刻掉。 所得的氮化物副产物是高度可溶的并且容易地在下列水性漂洗液中除去。 干燥步骤从集成电路中去除冲洗水。 最后，氧化物形成步骤提供相对纯的氧化物层。 在栅极氧化物的情况下，该方法除去用于栅极氧化物生长的牺牲氧化物。 在形成亚金属电介质的情况下，氧化物形成涉及TEOS氧化物沉积。 本发明的主要优点是由于硝酸而改善的钙去除。