公开(公告)号：US20100308863A1

公开(公告)日：2010-12-09

申请号：US12780772

申请日：2010-05-14

申请人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

发明人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/1735 ,  H01L27/11807

摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

摘要翻译： 集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。 布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。 此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

公开(公告)号：US07755110B2

公开(公告)日：2010-07-13

申请号：US11088506

申请日：2005-03-24

申请人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

发明人： Jörg Gliese ,  Winfried Kamp ,  Siegmar Köppe ,  Michael Scheppler

IPC分类号： H01L27/10

CPC分类号： H03K19/1735 ,  H01L27/11807

摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

摘要翻译： 集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。 布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。 此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

公开(公告)号：US07199618B2

公开(公告)日：2007-04-03

申请号：US10996620

申请日：2004-11-19

申请人： Jörg Gliese ,  Michael Scheppler

发明人： Jörg Gliese ,  Michael Scheppler

IPC分类号： H03K19/096

CPC分类号： H03K19/1737

摘要： A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a plurality of transistors of a first conduction type, and a plurality of control inputs coupled to the transistors.

摘要翻译： 一种逻辑电路装置，包括至少两个数据信号输入，在该数据信号输入端提供至少两个数据信号，耦合到数据信号输入的第一信号路径，并具有多个第一导电类型的晶体管和多个控制 耦合到晶体管的输入。

公开(公告)号：US07386812B2

公开(公告)日：2008-06-10

申请号：US10995960

申请日：2004-11-22

申请人： Jörg Gliese ,  Mirko Sauermann

发明人： Jörg Gliese ,  Mirko Sauermann

IPC分类号： G06F17/50

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： Logic basic cell and logic basic cell arrangement having a plurality of logic basic cells. A logic basic cell includes at least six data signal inputs, a first logic function block and a second logic function block, at least one logic function configuration input, a first multiplexer and a second multiplexer.

摘要翻译： 具有多个逻辑基本单元的逻辑基本单元和逻辑基本单元布置。 逻辑基本单元包括至少六个数据信号输入，第一逻辑功能块和第二逻辑功能块，至少一个逻辑功能配置输入，第一多路复用器和第二多路复用器。

公开(公告)号：US07279936B2

公开(公告)日：2007-10-09

申请号：US11007650

申请日：2004-12-07

申请人： Jörg Gliese ,  Tim Schönauer

发明人： Jörg Gliese ,  Tim Schönauer

IPC分类号： H03K19/20 ,  H03K19/084 ,  H03K19/21 ,  G11C8/00 ,  G06F7/50

CPC分类号： H03K19/17796 ,  H03K19/1736 ,  H03K19/17728

摘要： A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, having four data signal inputs, to which two data signals and the logically complementary data signals thereof can be applied, and having six logic selection elements between the data signal inputs. At a data signal output, the logic combination of the two data signals in accordance with the logic function selected by means of the logic selection elements can be provided as output signal.

摘要翻译： 逻辑基本单元，逻辑基本单元布置和逻辑器件。 逻辑基本单元被提供用于根据可以通过具有四个数据信号输入的多个逻辑选择元件选择的逻辑功能形成两个数据信号的逻辑组合，两个数据信号和逻辑互补 可以应用其数据信号，并且在数据信号输入之间具有六个逻辑选择元件。 在数据信号输出端，可以提供根据逻辑选择元件选择的逻辑功能的两个数据信号的逻辑组合作为输出信号。