公开(公告)号：US08598912B2

公开(公告)日：2013-12-03

申请号：US12815176

申请日：2010-06-14

申请人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

发明人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

IPC分类号： G01R19/00

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

公开(公告)号：US20110304358A1

公开(公告)日：2011-12-15

申请号：US12815176

申请日：2010-06-14

申请人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

发明人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

IPC分类号： H03F3/45

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

摘要翻译： 公开了用于预充电的感测放大器和方法，包括具有一对交叉耦合的互补晶体管反相器的读出放大器和一对晶体管，耦合到互补晶体管反相器中的相应一个的一对晶体管中的每一个， 。 感测放大器还包括耦合在该对晶体管之间的电容。 一种用于预充电的方法包括将读出放大器的输入节点耦合到预充电电压，将读出放大器的输入节点耦合在一起，并将电阻耦合到交叉耦合对的每个晶体管，以设置电压阈值（VT）失配补偿 每个晶体管的电压。 存储每个晶体管的VT失配补偿电压之间的电压差。

公开(公告)号：US07254074B2

公开(公告)日：2007-08-07

申请号：US11074518

申请日：2005-03-07

申请人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

发明人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

公开(公告)号：US07512025B2

公开(公告)日：2009-03-31

申请号：US12009521

申请日：2008-01-18

申请人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

发明人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

摘要翻译： 一种用于感测由存储器单元存储的数据状态的系统和方法，包括将第一数字线和第二数字线耦合到预充电电压，并进一步将存储单元耦合到第一数字线。 除了第一和第二数字线之外的至少一个数字线被驱动到参考电压电平，并且至少一个数字线耦合到第二数字线以在第二数字线中建立参考电压。 在第一数字线和第二数字线之间感测到电压差，并且响应地锁存基于电压差的数据状态。

公开(公告)号：US07460430B2

公开(公告)日：2008-12-02

申请号：US11497176

申请日：2006-08-01

申请人： Tae H. Kim ,  Charles L. Ingalls ,  Howard C. Kirsch ,  Jeremy J. Gum

发明人： Tae H. Kim ,  Charles L. Ingalls ,  Howard C. Kirsch ,  Jeremy J. Gum

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.

摘要翻译： 配置为减少存储器阵列中相邻字线之间的耦合噪声的存储器件。 更具体地说，字线驱动器被交错，使得相邻字线由不同行解码器启用的字线驱动器驱动。 每个字线驱动器包括一个微弱的晶体管接地和一个强大的晶体管接地。 通过禁用与​​有源字线直接相邻的字线上的字线驱动器，提供一个路径，以通过强晶体管驱动从有源字线到地的耦合噪声。

公开(公告)号：US20080137458A1

公开(公告)日：2008-06-12

申请号：US12009521

申请日：2008-01-18

申请人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

发明人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

摘要翻译： 一种用于感测由存储器单元存储的数据状态的系统和方法，包括将第一数字线和第二数字线耦合到预充电电压，并进一步将存储单元耦合到第一数字线。 除了第一和第二数字线之外的至少一个数字线被驱动到参考电压电平，并且至少一个数字线耦合到第二数字线以在第二数字线中建立参考电压。 在第一数字线和第二数字线之间感测到电压差，并且响应地锁存基于电压差的数据状态。

公开(公告)号：US06836427B2

公开(公告)日：2004-12-28

申请号：US10163404

申请日：2002-06-05

申请人： Huy T. Vo ,  Charles L. Ingalls ,  Howard C. Kirsch

发明人： Huy T. Vo ,  Charles L. Ingalls ,  Howard C. Kirsch

IPC分类号： G11C1124

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C11/4094

摘要： The disclosed system and method introduce voltage disturbances into a reference sub-array to offset voltage disturbances occurring in an active sub-array. The disclosed system and method connect extra, unused rows of memory cells to currently unused digitlines in the reference sub-array to cause surges that create voltage disturbances like those occurring in the active sub-array as a consequence of rows of memory cells in the active sub-array being connected to the active digitlines. As a result, when the sense amplifiers compare the voltages received on the active digitlines and the reference digitlines, the effects of the voltage disturbances on the active and reference digitlines lines offset each other.

摘要翻译： 所公开的系统和方法将电压干扰引入到参考子阵列中以消除在有源子阵列中出现的电压干扰。 所公开的系统和方法将额外的未使用的存储单元行连接到参考子阵列中的当前未使用的数字线，以引起诸如在有源子阵列中发生的电压扰动的浪涌，这是由于活动中的存储器单元的行的结果 子阵列连接到活动数字线。 结果，当读出放大器比较在有源数字线和参考数字线上接收的电压时，电压扰动对有源和参考数字线的影响彼此抵消。

公开(公告)号：US08737157B2

公开(公告)日：2014-05-27

申请号：US13298104

申请日：2011-11-16

申请人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

发明人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC分类号： G11C8/00 ,  G11C16/06

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20120063256A1

公开(公告)日：2012-03-15

申请号：US13298104

申请日：2011-11-16

申请人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

发明人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC分类号： G11C8/08 ,  H01L21/8239

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20110317509A1

公开(公告)日：2011-12-29

申请号：US13100874

申请日：2011-05-04

申请人： TAE KIM ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima

发明人： TAE KIM ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima

IPC分类号： G11C8/08 ,  H01L21/82

CPC分类号： H01L27/0207 ,  G11C8/08 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Each global word line driver includes at least one transistor of the first type. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 每个全局字线驱动器包括第一类型的至少一个晶体管。 公开了其他子系统和方法。