公开(公告)号：US20130026571A1

公开(公告)日：2013-01-31

申请号：US13194835

申请日：2011-07-29

申请人： JAMIL KAWA ,  VICTOR MOROZ ,  DEEPAK SHERLEKAR

发明人： JAMIL KAWA ,  VICTOR MOROZ ,  DEEPAK SHERLEKAR

IPC分类号： H01L27/12 ,  H01L21/82 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

摘要翻译： finFET块结构包括具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片。 在第一和第二组的外部散热片之间放置一个块间绝缘体。 图案化栅极导体层包括跨越第一块中的翅片集合延伸的第一多个栅极迹线，而不跨越块间绝缘体;以及第二多个栅极迹线，跨越第二块中的翅片组延伸，而不跨越 块间​​绝缘体。 栅极导体层上的图案化导体层以正交布局图案布置，并且包括布置成连接第一和第二块中的栅极迹线的块间连接器。

公开(公告)号：US20130125075A1

公开(公告)日：2013-05-16

申请号：US13731969

申请日：2012-12-31

申请人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

发明人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

IPC分类号： G06F17/50

CPC分类号： H01L21/823412 ,  G06F17/5036 ,  H01L21/823425 ,  H01L27/0207

摘要： An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

摘要翻译： 用于估计集成电路布局中阈值电压的布局引起的变化的自动化方法。 该方法开始于在布局内选择扩散区域以进行分析的步骤。 然后，系统识别所选区域的Si / STI边缘以及通道区域及其相关的栅极/ Si边缘。 接下来，识别每个识别的通道区域中的阈值电压变化，这需要由于纵向方向的影响而计算阈值电压变化的进一步步骤; 计算由于横向影响引起的阈值电压变化; 并且将纵向和横向变化组合以提供整体变化。 最后，通过组合来自各个通道变化的变化来确定总体变化。

公开(公告)号：US20090288049A1

公开(公告)日：2009-11-19

申请号：US12510938

申请日：2009-07-28

申请人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

发明人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

IPC分类号： G06F17/50

CPC分类号： H01L21/823412 ,  G06F17/5036 ,  H01L21/823425 ,  H01L27/0207

摘要： An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

摘要翻译： 用于估计集成电路布局中阈值电压的布局引起的变化的自动化方法。 该方法开始于在布局内选择扩散区域以进行分析的步骤。 然后，系统识别所选区域的Si / STI边缘以及通道区域及其相关的栅极/ Si边缘。 接下来，识别每个识别的通道区域中的阈值电压变化，这需要由于纵向方向的影响而计算阈值电压变化的进一步步骤; 计算由于横向影响引起的阈值电压变化; 并且将纵向和横向变化组合以提供整体变化。 最后，通过组合来自各个通道变化的变化来确定总体变化。

公开(公告)号：US20130334613A1

公开(公告)日：2013-12-19

申请号：US13495719

申请日：2012-06-13

申请人： VICTOR MOROZ

发明人： VICTOR MOROZ

IPC分类号： H01L27/088 ,  G06F17/50

CPC分类号： H01L27/0886 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/7848

摘要： A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor.

公开(公告)号：US20120280354A1

公开(公告)日：2012-11-08

申请号：US13101665

申请日：2011-05-05

申请人： VICTOR MOROZ ,  XI-WEI LIN

发明人： VICTOR MOROZ ,  XI-WEI LIN

IPC分类号： H01L29/02 ,  H01L21/302 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/3086

摘要： An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

摘要翻译： 描述了具有多条线的集成电路器件，其中线的宽度和相邻线之间的间距在小范围内变化，该范围独立于由于光刻工艺或其它图案化工艺引起的变化，其涉及制造 设备。 描述了用于形成用于线路的蚀刻掩模的顺序侧壁间隔物形成工艺，其导致以交替方式布置的第一组和第二组侧壁间隔件。 作为这种顺序侧壁间隔工艺的结果，跨越多条线的线的宽度的变化以及相邻线之间的间隔取决于侧壁间隔件的尺寸的变化。 这些变化与由图案化工艺引起的中间掩模元件的尺寸变化相比，分布远远小于分布，并且可以被控制。

公开(公告)号：US20110169140A1

公开(公告)日：2011-07-14

申请号：US12687358

申请日：2010-01-14

申请人： VICTOR MOROZ

发明人： VICTOR MOROZ

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV.

摘要翻译： 粗略地描述，集成电路器件包括：衬底，其包括穿过其中的通孔，通孔中的应变导电的第一材料，倾向于将第一应力引入衬底的第一材料和通孔中的应变的第二材料，第二材料 倾向于将至少部分地抵消第一应力的第二应力引入衬底。 在一个实施例中，SiGe在硅晶片中的通孔的内侧壁上外延生长。 然后在SiGe的内表面上形成SiO 2，并且在中心形成金属。 由SiGe引入的应力倾向于抵消由金属引入的应力，从而减少或消除硅中的不期望的应力，并允许将晶体管放置在TSV附近。

公开(公告)号：US20100029050A1

公开(公告)日：2010-02-04

申请号：US12577017

申请日：2009-10-09

申请人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

发明人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

IPC分类号： H01L21/336 ,  G06F17/50

CPC分类号： H01L21/823807 ,  H01L21/7624 ,  H01L29/7843

摘要： Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion.

公开(公告)号：US20100024978A1

公开(公告)日：2010-02-04

申请号：US12577021

申请日：2009-10-09

申请人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

发明人： VICTOR MOROZ ,  DIPANKAR PRAMANIK

IPC分类号： C23F1/08 ,  B05C11/00

CPC分类号： H01L21/823807 ,  H01L21/7624 ,  H01L29/7843

摘要： Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion.

摘要翻译： 改进的布局更好地利用所需的帽层诱导的横向和垂直应力。 在一个方面，粗略地描述，拉伸应变帽材料覆盖在N沟道扩散区域中的晶体管沟道上，但不覆盖P沟道扩散区域。 该材料终止于从N沟道扩散尽可能远地朝向P沟道扩散的边缘。 在另一方面，粗略地描述，栅极导体穿过P沟道扩散区域并且尽可能远地超过边缘终止，而不会与集成电路设计的任何其它特征产生不期望的电接触，并且不覆盖任何其它扩散区域。 压缩应变盖层覆盖P沟道扩散。 在另一方面，粗略地描述，栅极导体穿过N沟道扩散并在终止或转动之前延伸尽可能短的距离。 拉伸应变盖材料覆盖在N沟道扩散层上。

公开(公告)号：US20070298566A1

公开(公告)日：2007-12-27

申请号：US11851325

申请日：2007-09-06

申请人： VICTOR MOROZ ,  DIPANKAR PRAMANIK ,  XI-WEI LIN

发明人： VICTOR MOROZ ,  DIPANKAR PRAMANIK ,  XI-WEI LIN

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.

摘要翻译： 粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。 优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。 优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。