公开(公告)号：US20110095367A1

公开(公告)日：2011-04-28

申请号：US12605102

申请日：2009-10-23

申请人： Qing Su ,  Min Ni ,  Zongwu Tang ,  Jamil Kawa ,  James D. Sproch

发明人： Qing Su ,  Min Ni ,  Zongwu Tang ,  Jamil Kawa ,  James D. Sproch

IPC分类号： H01L27/06 ,  G06F17/50 ,  H01L21/336

CPC分类号： G06F17/5068 ,  H01L23/481 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0207 ,  H01L27/0255 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.

摘要翻译： 粗略地描述，天线二极管至少部分地形成在TSV周围的排阻区内，并且通过金属1层导体连接到TSV，同时TSV连接到栅极多晶硅或扩散层 放置在排除区外的一个或多个晶体管的区域。

公开(公告)号：US07260807B2

公开(公告)日：2007-08-21

申请号：US10734399

申请日：2003-12-12

申请人： Narendra V. Shenoy ,  Jamil Kawa ,  Raul Camposano

发明人： Narendra V. Shenoy ,  Jamil Kawa ,  Raul Camposano

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/64

摘要： One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect. During operation, the system receives a description of a mask-programmable cell, wherein instances of the mask-programmable cell are repeated to form the mask-programmable fabric. The system uses this description of the mask-programmable cell to generate a derived library containing cells that can be obtained by programming the mask-programmable cell. Next, the system receives a high-level design for the integrated circuit. The system then performs a synthesis operation on the high-level design to generate a preliminary netlist for the high-level design, wherein the preliminary netlist contains references to cells in the derived library. Finally, the system converts the preliminary netlist into a netlist that contains references to the mask-programmable cell with the logic appropriately programmed. The netlist is then placed and routed with the mask programmable constraints on the mask programmable fabric. The design, thus implemented on the programmable fabric, can be changed to accommodate logic revisions and bug fixes by changing only a few masks required for its fabrication.

摘要翻译： 本发明的一个实施例提供了一种使用包含掩模可编程逻辑和掩模可编程互连的掩码可编程结构来设计集成电路的系统。 在操作期间，系统接收掩模可编程单元的描述，其中重复掩模可编程单元的实例以形成掩模可编程结构。 该系统使用掩模可编程单元的描述来生成包含可通过对掩模可编程单元进行编程而获得的单元的导出库。 接下来，系统接收集成电路的高级设计。 然后，系统对高级设计执行合成操作，以生成高级设计的初步网表，其中初步网表包含对派生库中的单元的引用。 最后，系统将初步网表转换成网表，其中包含对具有适当编程逻辑的掩码可编程单元的引用。 然后将网表与面罩可编程织物上的掩码可编程约束放置和布线。 通过改变其制造所需的几个掩模，可以改变在可编程结构上实现的设计，以适应逻辑修订和错误修复。

公开(公告)号：US09287253B2

公开(公告)日：2016-03-15

申请号：US13374335

申请日：2011-12-22

申请人： Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

发明人： Victor Moroz ,  Jamil Kawa ,  James D. Sproch ,  Robert B. Lefferts

IPC分类号： H01L27/02 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

摘要： In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

公开(公告)号：US20140061936A1

公开(公告)日：2014-03-06

申请号：US13601394

申请日：2012-08-31

申请人： Victor Moroz ,  Jamil Kawa

发明人： Victor Moroz ,  Jamil Kawa

IPC分类号： H01L23/48 ,  G06F17/50 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/48 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/16238 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.

公开(公告)号：US08561003B2

公开(公告)日：2013-10-15

申请号：US13194835

申请日：2011-07-29

申请人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

发明人： Jamil Kawa ,  Victor Moroz ,  Deepak Sherlekar

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

摘要翻译： finFET块结构包括具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片。 在第一和第二组的外部散热片之间放置一个块间绝缘体。 图案化栅极导体层包括跨越第一块中的翅片集合延伸的第一多个栅极迹线，而不跨越块间绝缘体;以及第二多个栅极迹线，跨越第二块中的翅片组延伸，而不会穿过第 块间​​绝缘体。 栅极导体层上的图案化导体层以正交布局图案布置，并且包括布置成连接第一和第二块中的栅极迹线的块间连接器。

公开(公告)号：US08176456B2

公开(公告)日：2012-05-08

申请号：US12343958

申请日：2008-12-24

申请人： Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

发明人： Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation.

摘要翻译： 本发明的一个实施例提供了一种计算CMP（化学机械抛光）工艺的虚拟特征密度的系统。 请注意，虚拟特征密度用于向布局添加虚拟特征以减少CMP后的拓扑变化。 在操作期间，系统将集成电路的布局离散成多个面板。 接下来，系统计算多个面板的特征密度和松弛密度。 然后，系统通过迭代地计算多个面板的虚拟特征密度，（a）使用特征密度计算多个面板的有效特征密度，以及对CMP过程建模的功能，（b）计算填充量 对于使用目标特征密度，有效特征密度和松弛密度的多个面板中的一组面板，以及（c）更新该组面板的特征密度，松弛密度和虚拟特征密度，使用 填充量。 在本发明的一个实施例中，迭代过程由方差最小化启发式引导，以有效地选择面板集合并且将虚空密度分配/去除到该组面板以减小有效特征密度变化。

公开(公告)号：US20100014199A1

公开(公告)日：2010-01-21

申请号：US12176801

申请日：2008-07-21

申请人： Jamil Kawa ,  Subarnarekha Sinha ,  Min-Chun Tsai ,  ZongWu Tang ,  Qing Su

发明人： Jamil Kawa ,  Subarnarekha Sinha ,  Min-Chun Tsai ,  ZongWu Tang ,  Qing Su

IPC分类号： H02H9/04 ,  G06F17/50

CPC分类号： H01L27/0251 ,  H01H59/0009

摘要： Embodiments of an interface circuit are described. This interface circuit includes an input pad, a control node and a transistor, which has three terminals. A first terminal is electrically coupled to the input pad and a second terminal is electrically coupled to the control node. Moreover, the interface circuit includes a micro-electromechanical system (MEMS) switch, which is electrically coupled to the input pad and the control node, where the MEMS switch is in parallel with the transistor. In the absence of a voltage applied to a control terminal of the MEMS switch, the MEMS switch is closed, thereby electrically coupling the input pad and the control node. Furthermore, when the voltage is applied to the control terminal of the MEMS switch, the MEMS switch is open, thereby electrically decoupling the input pad and the control node.

摘要翻译： 描述接口电路的实施例。 该接口电路包括具有三个端子的输入焊盘，控制节点和晶体管。 第一端子电耦合到输入焊盘，并且第二端子电耦合到控制节点。 此外，接口电路包括微机电系统（MEMS）开关，其电耦合到输入焊盘和控制节点，其中MEMS开关与晶体管并联。 在没有施加到MEMS开关的控制端子的电压的情况下，MEMS开关闭合，从而电耦合输入焊盘和控制节点。 此外，当将电压施加到MEMS开关的控制端子时，MEMS开关断开，由此使输入焊盘和控制节点电耦合。

公开(公告)号：US20080278191A1

公开(公告)日：2008-11-13

申请号：US12179555

申请日：2008-07-24

申请人： Jamil Kawa

发明人： Jamil Kawa

IPC分类号： H03K17/16

CPC分类号： H03K19/0013 ,  G11C11/417 ,  H03K19/0016

摘要： A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

摘要翻译： 公开了一种使逻辑块中的亚阈值泄漏最小化的方法和系统。 NDR隔离装置耦合在逻辑块和地之间以形成虚拟接地节点。 为了将逻辑块置于睡眠模式，虚拟地面控制装置将虚拟接地节点处的电压提高到隔离电压以上，这使得NDR隔离装置将虚拟接地节点与地相隔离。 然后，虚拟地面控制装置可以将虚拟接地节点处的电压升高到正电源电压，以消除逻辑块的次阈值泄漏电流。 或者，虚拟地面控制装置可以将虚拟接地节点处的电压提高到正电源电压减去保持电压，使得逻辑块中的存储元件可以保持状态信息，同时仍大大降低子阈值泄漏电流。

公开(公告)号：US07417451B2

公开(公告)日：2008-08-26

申请号：US11245933

申请日：2005-10-07

申请人： Jamil Kawa

发明人： Jamil Kawa

IPC分类号： H03K17/16

CPC分类号： H03K19/0013 ,  G11C11/417 ,  H03K19/0016

摘要： A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

摘要翻译： 公开了一种使逻辑块中的亚阈值泄漏最小化的方法和系统。 NDR隔离装置耦合在逻辑块和地之间以形成虚拟接地节点。 为了将逻辑块置于睡眠模式，虚拟地面控制装置将虚拟接地节点处的电压提高到隔离电压以上，这使得NDR隔离装置将虚拟接地节点与地相隔离。 然后，虚拟地面控制装置可以将虚拟接地节点处的电压升高到正电源电压，以消除逻辑块的次阈值泄漏电流。 或者，虚拟地面控制装置可以将虚拟接地节点处的电压提高到正电源电压减去保持电压，使得逻辑块中的存储元件可以保持状态信息，同时仍大大降低子阈值泄漏电流。

公开(公告)号：US5146306A

公开(公告)日：1992-09-08

申请号：US638629

申请日：1991-01-08

申请人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  James S. Hsue

发明人： Thomas V. Ferry ,  Jamil Kawa ,  Kerry M. Pierce ,  William G. Walker ,  James S. Hsue

IPC分类号： H03K19/003

CPC分类号： H03K19/00361

摘要： Slew-rate control is implemented in input/output device structures where MOSFETs are employed to switch the output signal. These MOSFETs each have a substrate, an insulating layer adjacent to the substrate and a strip of semiconductor material separated from the substrate by the insulating layer. The strip of semiconductor material functions as the gate of the MOSFET. The strip of semiconductor material does not form a closed loop. One end of the strip of a first transistor is connected to one end of the strip of the second transistor. Thus, the gates of the two transistors are placed in series so that they are not switched on at the same time. A delay is thereby automatically introduced between the switching on of the two transistors. The delay is controlled by placing metal straps across selected transistor gates to effectively bypass the delays caused by the current propagating through the gates. Further control of the delay is gained by use of a feedback signal to increase or decrease the current in the gates.

摘要翻译： 在使用MOSFET来切换输出信号的输入/输出器件结构中实现压摆率控制。 这些MOSFET各自具有基板，与基板相邻的绝缘层和通过绝缘层与基板分离的半导体材料条。 半导体材料条作为MOSFET的栅极起作用。 半导体材料条不形成闭环。 第一晶体管的条的一端连接到第二晶体管的条的一端。 因此，两个晶体管的栅极被串联放置，使得它们不被同时接通。 因此在两个晶体管的接通之间自动引入延迟。 通过将金属带放置在选定的晶体管栅极上来有效地绕过由栅极传播的电流引起的延迟来控制延迟。 通过使用反馈信号来增加或减少门中的电流来获得延迟的进一步控制。