公开(公告)号：US08813012B2

公开(公告)日：2014-08-19

申请号：US13550460

申请日：2012-07-16

申请人： Michael L. Rieger ,  Victor Moroz

发明人： Michael L. Rieger ,  Victor Moroz

IPC分类号： G06F17/50

CPC分类号： H01L23/5226 ,  G06F17/5072 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.

摘要翻译： 通过使用松弛图案曝光的互连自对准。 根据第一方法实施例，一种用于控制用于设计集成电路的物理特征的计算机辅助设计（CAD）系统的方法包括：访问用于第一金属层上的第一金属迹线的第一图案，访问用于第二金属层的第二图案 垂直于第一金属层的第二金属层上的金属迹线，并且访问第一和第二金属迹线之间的预期互连的精确图案。 操作预定互连的精确模式以形成指示允许通孔的多个通用区域的不精确的通孔图案。 通过图案的不精确性用于集成电路制造过程中，与形成第一和第二金属层的操作一起形成用于互连预期互连的多个自对准通孔。

公开(公告)号：US08762924B2

公开(公告)日：2014-06-24

申请号：US12510188

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

摘要翻译： 粗略地描述了一种用于近似集成电路布局中的沟道区域中的应力诱导迁移率增强的方法，包括近似在通道中的多个采样点中的每一个处的应力，将每个采样点处的应力近似转换为 相应的移动性增强值，并在所有采样点平均移动性增强值。 该方法实现了集成电路应力分析，其考虑了由多个应力产生机制所产生的应力，具有沿通道长度以外的矢量分量的应力，以及由于在邻域中存在其它结构的应力贡献（包括缓解） 正在研究的频道区域，除了最接近的STI接口。 该方法还能够对大型布局区域甚至全芯片布局进行应力分析，而不会导致完整TCAD仿真的计算成本。

公开(公告)号：US08713510B2

公开(公告)日：2014-04-29

申请号：US12510185

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US08407634B1

公开(公告)日：2013-03-26

申请号：US11291294

申请日：2005-12-01

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F9/45

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US20130026575A1

公开(公告)日：2013-01-31

申请号：US13193320

申请日：2011-07-28

申请人： Victor Moroz ,  James D. Sproch

发明人： Victor Moroz ,  James D. Sproch

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/78618

摘要： Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff.

摘要翻译： 粗略地描述，集成电路器件已经在衬底上形成多个晶体管，其包括至少一个晶体管的第一子集和至少一个晶体管的第二子集，其中第一子集中的所有晶体管具有一个下层距离，并且全部 的第二子集中的晶体管具有不同的底层距离。 第一和第二子集中的晶体管优选地具有不同的阈值电压，并且优选地在高性能/低功率权衡上实现不同的点。

公开(公告)号：US20130026571A1

公开(公告)日：2013-01-31

申请号：US13194835

申请日：2011-07-29

申请人： JAMIL KAWA ,  VICTOR MOROZ ,  DEEPAK SHERLEKAR

发明人： JAMIL KAWA ,  VICTOR MOROZ ,  DEEPAK SHERLEKAR

IPC分类号： H01L27/12 ,  H01L21/82 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

摘要翻译： finFET块结构包括具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片。 在第一和第二组的外部散热片之间放置一个块间绝缘体。 图案化栅极导体层包括跨越第一块中的翅片集合延伸的第一多个栅极迹线，而不跨越块间绝缘体;以及第二多个栅极迹线，跨越第二块中的翅片组延伸，而不跨越 块间​​绝缘体。 栅极导体层上的图案化导体层以正交布局图案布置，并且包括布置成连接第一和第二块中的栅极迹线的块间连接器。

公开(公告)号：US20120280354A1

公开(公告)日：2012-11-08

申请号：US13101665

申请日：2011-05-05

申请人： VICTOR MOROZ ,  XI-WEI LIN

发明人： VICTOR MOROZ ,  XI-WEI LIN

IPC分类号： H01L29/02 ,  H01L21/302 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/3086

摘要： An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

摘要翻译： 描述了具有多条线的集成电路器件，其中线的宽度和相邻线之间的间距在小范围内变化，该范围独立于由于光刻工艺或其它图案化工艺引起的变化，其涉及制造 设备。 描述了用于形成用于线路的蚀刻掩模的顺序侧壁间隔物形成工艺，其导致以交替方式布置的第一组和第二组侧壁间隔件。 作为这种顺序侧壁间隔工艺的结果，跨越多条线的线的宽度的变化以及相邻线之间的间隔取决于侧壁间隔件的尺寸的变化。 这些变化与由图案化工艺引起的中间掩模元件的尺寸变化相比，分布远远小于分布，并且可以被控制。

公开(公告)号：US08086990B2

公开(公告)日：2011-12-27

申请号：US12433759

申请日：2009-04-30

申请人： Xi-Wei Lin ,  Victor Moroz ,  Dipankar Pramanik

发明人： Xi-Wei Lin ,  Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.

摘要翻译： 粗略描述，可以通过替代不同的应力分析器来更好地模拟晶体管的应力调整特性来修改标准SPICE模型。 第一，标准，应力敏感的晶体管模型用于开发第一晶体管性能测量与可用作第二，不应力敏感晶体管模型的输入的一个或多个实例参数之间的数学关系。 第二晶体管模型可以例如与第一模型相同，其应力灵敏度被禁用。 此后，可以使用替代应力分析器来确定用于第一性能测量的应力调整值，并且可以使用数学关系将该值转换为一个或多个实例参数的特定值。 然后将这些值提供给第二晶体管模型，以用于在电路仿真期间模拟特定晶体管的特性。

公开(公告)号：US20110219351A1

公开(公告)日：2011-09-08

申请号：US13112837

申请日：2011-05-20

申请人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.

摘要翻译： 用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。 该方法的第一步是从阵列中选择一个用于分析的晶体管。 该方法根据需要在阵列的晶体管之间循环。 接下来分析所选择的晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。 该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。 该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

公开(公告)号：US20110212601A1

公开(公告)日：2011-09-01

申请号：US13103677

申请日：2011-05-09

申请人： Victor Moroz ,  Tsu-Jae King Liu

发明人： Victor Moroz ,  Tsu-Jae King Liu

IPC分类号： H01L21/20

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7843

摘要： Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

摘要翻译： 提供了基于表面/通道方向和应变封盖层类型的FinFET性能增强的不同方法。 在提供性能提升的一种相对简单和便宜的方法中，可以将n沟道FinFET（nFinFET）和p沟道FinFET（pFinFET）用于单个表面/沟道方向取向和单个应变封装层。 在包括更多工艺步骤（从而增加制造成本）但提供显着更高性能提升的另一种方法中，不同的表面/沟道方向取向和不同的应变封装层可用于nFinFET和pFinFET。