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公开(公告)号：US20130145229A1
公开(公告)日：2013-06-06
申请号：US13679963
申请日：2012-11-16
IPC分类号： H03M13/29
CPC分类号： H03M13/2903 , G06F11/1012
摘要： An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments. Further, the system includes a controller configured to provide the two or more first data segments of the data word to the first encoder for encoding and to provide the one or more second data segments of the data word to the second encoder for encoding.
摘要翻译： 错误控制编码系统从数据字产生码字，其中所得到的码字包括数据字和使用数据字产生的三个或更多个奇偶校验段。 该系统包括第一编码器，用于对两个或更多个第一数据段中的数据字进行编码，以便产生两个或更多个第一奇偶校验段，其中两个或更多个第一数据段中的每一个包括数据字的相应顺序部分。 该系统包括第二编码器，用于对一个或多个第二数据段中的数据字进行编码，以便产生对应的一个或多个第二奇偶校验段，其中一个或多个第二数据段中的每一个包括数据字的相应顺序部分 并且所述一个或多个第二数据段中的每一个还包括包含在多个所述两个或更多个第一数据段中的所述数据的顺序部分。 此外，该系统包括控制器，其被配置为将数据字的两个或更多个第一数据段提供给第一编码器进行编码，并将数据字的一个或多个第二数据段提供给第二编码器进行编码。
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2.发明申请Systems, Methods and Devices for Decoding Codewords Having Multiple Parity Segments 有权用于解码具有多个奇偶校验段的码字的系统，方法和设备公开(公告)号：US20130132804A1
公开(公告)日：2013-05-23
申请号：US13679969
申请日：2012-11-16
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , G06F11/1012
摘要： An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module.
摘要翻译： 错误控制解码系统对包含数据字和两个或多个奇偶校验段的码字进行解码。 该系统包括第一解码器，通过利用一个或多个第一奇偶校验段和包括在码字中的数据字来解码码字，以及第二解码器，通过利用一个或多个第二奇偶校验段和包括在该字符串中的数据字对码字进行解码 码字，其中所述一个或多个第一奇偶校验段与所述一个或多个第二奇偶校验段不同。 误差估计模块估计码字中的错误数，并且控制器选择第一解码器和第二解码器中的哪个解码器开始对码字进行解码，其中所述选择是基于由所述码字提供的码字中的错误数量的估计 误差估计模块
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公开(公告)号：US20130145231A1
公开(公告)日：2013-06-06
申请号：US13679970
申请日：2012-11-16
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , G06F11/1012 , H03M13/1102 , H03M13/152 , H03M13/2906 , H03M13/2948 , H03M13/356
摘要： An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.
摘要翻译： 错误控制系统使用对应于存储介质的错误密度位置简档的错误控制代码。 该系统包括编码器，其被配置为使用与存储介质的误差密度位置分布相对应的误差控制码发生器矩阵从数据产生一个或多个码字。 该系统还包括解码器，其被配置为使用对应于存储介质的误差密度位置简档的误差控制码奇偶校验矩阵从一个或多个码字产生解码数据，其中奇偶校验矩阵的列与相应的数据相关联 存储介质的位，奇偶校验矩阵的行与校验位相关联，并且具有预定义值的奇偶校验矩阵的每个矩阵元素指示特定数据位和特定校验位之间的连接。
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4.发明授权公开(公告)号：US08954822B2
公开(公告)日：2015-02-10
申请号：US13679970
申请日：2012-11-16
CPC分类号： H03M13/13 , G06F11/1012 , H03M13/1102 , H03M13/152 , H03M13/2906 , H03M13/2948 , H03M13/356
摘要： An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.
摘要翻译： 错误控制系统使用对应于存储介质的错误密度位置简档的错误控制代码。 该系统包括编码器，其被配置为使用与存储介质的误差密度位置分布相对应的误差控制码发生器矩阵从数据产生一个或多个码字。 该系统还包括解码器，其被配置为使用对应于存储介质的误差密度位置简档的误差控制码奇偶校验矩阵从一个或多个码字产生解码数据，其中奇偶校验矩阵的列与相应的数据相关联 存储介质的位，奇偶校验矩阵的行与校验位相关联，并且具有预定义值的奇偶校验矩阵的每个矩阵元素指示特定数据位和特定校验位之间的连接。
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公开(公告)号：US08621138B2
公开(公告)日：2013-12-31
申请号：US12082223
申请日：2008-04-08
申请人： Aaron K. Olbrich , Douglas A. Prins
发明人： Aaron K. Olbrich , Douglas A. Prins
IPC分类号： G06F12/02
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F13/1657 , G06F13/28 , G06F2212/7201 , G11C7/1051 , G11C7/1063 , G11C16/10
摘要： In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed.
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公开(公告)号：US08621137B2
公开(公告)日：2013-12-31
申请号：US12082222
申请日：2008-04-08
申请人： Aaron K. Olbrich , Douglas A. Prins
发明人： Aaron K. Olbrich , Douglas A. Prins
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F13/1657 , G06F13/28 , G06F2212/7201 , G11C7/1051 , G11C7/1063 , G11C16/10
摘要： A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid.
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7.发明授权Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories 有权用于闪存的存储控制器，包括连接多个处理器与多个内部存储器的交叉开关公开(公告)号：US08775717B2
公开(公告)日：2014-07-08
申请号：US12082207
申请日：2008-04-08
申请人： Douglas A. Prins , Aaron K. Olbrich
发明人： Douglas A. Prins , Aaron K. Olbrich
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F13/1657 , G06F13/28 , G06F2212/7201 , G11C7/1051 , G11C7/1063 , G11C16/10
摘要： A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.
摘要翻译： 设计用于与闪存存储模块一起使用的控制器，包括设计成将多个内部处理器与包含多个内部存储器的各种内部资源连接的交叉开关。 这些记忆包含处理器的工作列表。 在一个实施例中，处理器通过使用交叉开关将任务放置在其他处理器的工作列表上进行通信。
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8.发明授权Mass storage controller volatile memory containing metadata related to flash memory storage 有权大容量存储控制器包含与闪存存储有关的元数据的易失性存储器公开(公告)号：US08751755B2
公开(公告)日：2014-06-10
申请号：US12082206
申请日：2008-04-08
申请人： Douglas A. Prins , Aaron K. Olbrich
发明人： Douglas A. Prins , Aaron K. Olbrich
IPC分类号： G06F12/02
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F13/1657 , G06F13/28 , G06F2212/7201 , G11C7/1051 , G11C7/1063 , G11C16/10
摘要： A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata.
摘要翻译： 与大容量存储控制器和闪存模块相关联的易失性存储器。 易失性存储器包括包含与闪存存储器相关的信息的多个表，包括存储物理闪存地址的表和包含元数据的多个表。
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公开(公告)号：US08484534B2
公开(公告)日：2013-07-09
申请号：US13535243
申请日：2012-06-27
申请人： Aaron K. Olbrich , Doug Prins
发明人： Aaron K. Olbrich , Doug Prins
IPC分类号： G11C29/00
CPC分类号： G11C16/22 , G06F11/1012 , G06F11/1044
摘要： In a multiple level cell flash memory data storage device, a flash memory array has a plurality of blocks, where each block is an erase unit and has a plurality of pages, and a respective block includes a plurality of groups of pages. Each group of pages in the respective block includes an assigned parity page, and each page of the respective block has a plurality of sectors, including an assigned parity sector. The storage device is operable to program and erase data on a page at a predetermined speed, and detect an error rate for each page of a block and identify a group of high error pages based on the error rates. Further, the storage device is configured to apply a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.
摘要翻译： 在多级单元闪存数据存储设备中，闪存阵列具有多个块，其中每个块是擦除单元并且具有多个页，并且相应块包括多个页组。 相应块中的每组页包括分配的奇偶校验页，并且相应块的每一页具有多个扇区，包括分配的奇偶校验扇区。 存储装置可操作以预定速度对页面上的数据进行编程和擦除，并且检测块的每个页面的错误率，并基于错误率识别一组高错误页面。 此外，存储装置被配置为施加比预定速度慢的速度来编程和擦除所识别的高错误页面上的数据。
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公开(公告)号：US08365041B2
公开(公告)日：2013-01-29
申请号：US12726200
申请日：2010-03-17
申请人： Aaron K. Olbrich , Doug Prins
发明人： Aaron K. Olbrich , Doug Prins
IPC分类号： G11C29/00
CPC分类号： G11C16/22 , G06F11/1012 , G06F11/1044
摘要： A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
摘要翻译： 一种在MLC多级单元闪存设备中保护基于页面的存储数据的二维自RAID方法。 保护方案包括在每个数据页面上保留一个奇偶校验扇区，将一个奇偶校验页面保留为列奇偶校验，选择特定页数以形成奇偶校验组，向奇偶校验页写入存储在页面中的数据的组奇偶校验值 奇偶校验组。 奇偶校验扇区表示在第一维中应用RAID技术。 组奇偶校验表示在第二维中应用RAID技术。 实现数据保护是因为二维RAID数据可能会恢复损坏的数据扇区。
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