-
公开(公告)号:US20190205273A1
公开(公告)日:2019-07-04
申请号:US16146534
申请日:2018-09-28
申请人: Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
发明人: Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
IPC分类号: G06F13/16 , H01L25/18 , G11C11/419 , G11C11/408 , H01L23/522 , H03K19/21
摘要: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
-
公开(公告)号:US20190080731A1
公开(公告)日:2019-03-14
申请号:US16124068
申请日:2018-09-06
申请人: Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
发明人: Jack KAVALIEROS , Ram KRISHNAMURTHY , Sasikanth MANIPATRUNI , Gregory CHEN , Van LE , Amrita MATHURIYA , Abhishek SHARMA , Raghavan KUMAR , Phil KNAG , Huseyin SUMBUL
摘要: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
-