公开(公告)号：US20190205273A1

公开(公告)日：2019-07-04

申请号：US16146534

申请日：2018-09-28

申请人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

发明人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC分类号： G06F13/16 ,  H01L25/18 ,  G11C11/419 ,  G11C11/408 ,  H01L23/522 ,  H03K19/21

摘要： Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US20190080731A1

公开(公告)日：2019-03-14

申请号：US16124068

申请日：2018-09-06

申请人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

发明人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC分类号： G11C7/10 ,  G11C11/56 ,  G11C7/18

摘要： Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US20190042159A1

公开(公告)日：2019-02-07

申请号：US16146878

申请日：2018-09-28

申请人： Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

发明人： Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

IPC分类号： G06F3/06 ,  H03K3/03 ,  G11C7/10

摘要： Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.

公开(公告)号：US20200098824A1

公开(公告)日：2020-03-26

申请号：US16142040

申请日：2018-09-26

申请人： Abhishek SHARMA ,  Gregory K. CHEN ,  Ram KRISHNAMURTHY ,  Ravi PILLARISETTY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Urusa ALAAN ,  Noriyuki SATO

发明人： Abhishek SHARMA ,  Gregory K. CHEN ,  Ram KRISHNAMURTHY ,  Ravi PILLARISETTY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Urusa ALAAN ,  Noriyuki SATO

IPC分类号： H01L27/24 ,  H01L45/00

摘要： Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a substrate, a RRAM storage cell above the substrate, and a diode adjacent to the RRAM storage cell. The RRAM storage cell includes a first electrode located in a first metal layer above the substrate, a resistive switching material layer adjacent to the first electrode, and a second electrode adjacent to the resistive switching material layer. The second electrode is shared between the RRAM storage cell and the diode. The diode includes the second electrode shared with the RRAM storage cell, a semiconductor layer adjacent to the second electrode, and a third electrode located in a second metal layer above the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20190103156A1

公开(公告)日：2019-04-04

申请号：US16146932

申请日：2018-09-28

申请人： Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil Ekin KNAG ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram A. KRISHNAMURTHY ,  Ian A. YOUNG

发明人： Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Phil Ekin KNAG ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram A. KRISHNAMURTHY ,  Ian A. YOUNG

IPC分类号： G11C11/419

CPC分类号： G11C11/419 ,  G11C7/1006 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  G11C27/024

摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

公开(公告)号：US20160248427A1

公开(公告)日：2016-08-25

申请号：US14129527

申请日：2013-09-11

申请人： Dmitri E. NIKONOV ,  Sasikanth MANIPATRUNI ,  Ian A. YOUNG ,  Vehbi CALAYIR

发明人： Dmitri E. NIKONOV ,  Sasikanth MANIPATRUNI ,  Ian A. YOUNG ,  Vehbi CALAYIR

IPC分类号： H03K19/16 ,  G06F7/501 ,  H03K19/20

CPC分类号： H03K19/16 ,  B82Y25/00 ,  G06F7/501 ,  G11C11/161 ,  H03K3/45 ,  H03K19/20

摘要： Described is a latch comprising: a first all-spin logic (ASL) device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a clock signal; and a third ASL device coupled to the second ASL device, wherein the first and third ASL devices have respective magnets coupled to a power supply terminal. Described is a flip-flop which comprises: a first ASL device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a first clock signal; a third ASL device coupled to the second ASL device, the third ASL device controllable by a second clock signal, the second clock signal being out of phase relative to the first clock signal; and a fourth ASL device coupled to the third ASL device, wherein the first and fourth ASL devices have respective magnets coupled to a power supply terminal.

摘要翻译： 描述了一种锁存器，包括：第一全自旋逻辑（ASL）装置; 耦合到所述第一ASL设备的第二ASL设备，所述第二ASL设备可由时钟信号控制; 以及耦合到所述第二ASL装置的第三ASL装置，其中所述第一和第三ASL装置具有耦合到电源端子的相应磁体。 描述了一种触发器，其包括：第一ASL装置; 耦合到所述第一ASL设备的第二ASL设备，所述第二ASL设备可由第一时钟信号控制; 耦合到所述第二ASL装置的第三ASL装置，所述第三ASL装置可由第二时钟信号控制，所述第二时钟信号相对于所述第一时钟信号异相; 以及耦合到所述第三ASL装置的第四ASL装置，其中所述第一和第四ASL装置具有耦合到电源端子的相应磁体。

公开(公告)号：US20200006516A1

公开(公告)日：2020-01-02

申请号：US16024719

申请日：2018-06-29

申请人： Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Seiyon KIM ,  Ian YOUNG

发明人： Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Seiyon KIM ,  Ian YOUNG

IPC分类号： H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L49/02 ,  H01L29/786

摘要： An integrated circuit structure comprises a substrate. An antiferroelectric gate oxide is above the substrate, the antiferroelectric gate oxide comprising a perovskite material. A gate electrode is over at least a portion of the gate oxide.

公开(公告)号：US20160300612A1

公开(公告)日：2016-10-13

申请号：US15036761

申请日：2013-12-24

申请人： Sasikanth MANIPATRUNI ,  Ian A. YOUNG ,  INTEL CORPORATION

发明人： Sasikanth MANIPATRUNI ,  Ian A. YOUNG

IPC分类号： G11C14/00 ,  G11C11/16 ,  H01L27/108 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C13/00 ,  H01L27/22

CPC分类号： G11C14/0036 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0069 ,  G11C14/0018 ,  G11C14/0045 ,  H01L27/10832 ,  H01L27/1087 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H04L9/0897

摘要： Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.

摘要翻译： 描述了一种用于混合eDRAM和MRAM存储单元的装置，包括：具有第一端子和第二端子的电容器; 第一晶体管，其具有耦合到第一字线（WL）的栅极端子，耦合到位线（BL）的源极/漏极端子以及耦合到所述电容器的所述第一端子的漏极/源极端子; 具有第一端子和第二端子的电阻性存储元件，所述电阻式存储元件器件的所述第一端子耦合到所述电容器的第一端子; 以及第二晶体管，其具有耦合到第二WL的栅极端子，耦合到源极线（SL）的源极/漏极端子以及耦合到所述电阻性存储器件器件的所述第二端子的漏极/源极端子。

公开(公告)号：US20200091407A1

公开(公告)日：2020-03-19

申请号：US16130905

申请日：2018-09-13

申请人： Huichu LIU ,  Tanay KARNIK ,  Sasikanth MANIPATRUNI ,  Daniel MORRIS ,  Kaushik VAIDYANATHAN ,  Ian YOUNG

发明人： Huichu LIU ,  Tanay KARNIK ,  Sasikanth MANIPATRUNI ,  Daniel MORRIS ,  Kaushik VAIDYANATHAN ,  Ian YOUNG

IPC分类号： H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18 ,  H01L43/06

摘要： An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.