公开(公告)号：US20190205273A1

公开(公告)日：2019-07-04

申请号：US16146534

申请日：2018-09-28

申请人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

发明人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC分类号： G06F13/16 ,  H01L25/18 ,  G11C11/419 ,  G11C11/408 ,  H01L23/522 ,  H03K19/21

摘要： Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US20190080731A1

公开(公告)日：2019-03-14

申请号：US16124068

申请日：2018-09-06

申请人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

发明人： Jack KAVALIEROS ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory CHEN ,  Van LE ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL

IPC分类号： G11C7/10 ,  G11C11/56 ,  G11C7/18

摘要： Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

公开(公告)号：US20190057300A1

公开(公告)日：2019-02-21

申请号：US16160466

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06N3/04 ,  G06F3/06 ,  G06F12/0875

摘要： The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

公开(公告)号：US20190057036A1

公开(公告)日：2019-02-21

申请号：US16160270

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06

摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

公开(公告)号：US20100327842A1

公开(公告)日：2010-12-30

申请号：US12823160

申请日：2010-06-25

申请人： Mingoo Seok ,  Dennis Sylvester ,  David Blaauw ,  Scott Hanson ,  Gregory Chen

发明人： Mingoo Seok ,  Dennis Sylvester ,  David Blaauw ,  Scott Hanson ,  Gregory Chen

IPC分类号： G05F3/16

CPC分类号： G05F3/242

摘要： An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.

摘要翻译： 提供改进的电压基准发生器。 所述电压参考发生器包括：第一晶体管，具有被偏置以将所述第一晶体管置于弱反相模式的栅电极; 以及与所述第一晶体管串联连接的第二晶体管，并且具有被偏置以将所述第二晶体管置于弱反相模式的栅电极，其中所述第一晶体管的阈值电压小于所述第二晶体管和所述栅电极的阈值电压 的第二晶体管的电极电耦合到第二晶体管的漏电极和第一晶体管的源电极，以形成用于参考电压的输出。

公开(公告)号：US20190057050A1

公开(公告)日：2019-02-21

申请号：US16160952

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC分类号： G06F13/16 ,  G06F13/28

摘要： Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US4536814A

公开(公告)日：1985-08-20

申请号：US593324

申请日：1984-03-26

申请人： Peter J. Theisen ,  C. Gregory Chen

发明人： Peter J. Theisen ,  C. Gregory Chen

IPC分类号： H01H9/10 ,  H01H9/54 ,  H01H33/59 ,  H01H33/14

CPC分类号： H01H33/596 ,  H01H9/10 ,  H01H9/542

摘要： A D.C. power controller for interrupting a high voltage high current D.C. power line supplying a load (L) from a D.C. power supply source (+270VDC) having power contacts (CCC, AC), actuator means (MA, SA) for operating the power contacts (CCC, AC), arc extinguishing means (AH1, AH2, AS1, AS2), arc shunting solid state elements (SSC) for receiving the arc current from the power contacts, electronic control means (CE) for controlling the actuator means, protective means comprising a fuse (F) and fuse shunt contacts (FSC) in parallel in the power line, and the electronic control means (CE) controlling the actuator means (MA, SA) to close first and open last the fuse shunt contacts with respect to the power contacts so that the fuse will blow to interrupt the power line in the event either the power contacts or the solid state elements fail to do so, and the electronic control means being supplied with power through the fuse to disable the same when the fuse blows so that the load cannot be reenergized before the fault is corrected.

摘要翻译： 一种直流电力控制器，用于中断从具有电源触点（CCC，AC）的直流电源（+ 270VDC），用于操作电力的致动器装置（MA，SA）提供负载（L）的高压大电流直流电力线 触点（CCC，AC），灭弧装置（AH1，AH2，AS1，AS2），用于接收来自电源触点的电弧电流的电弧分流固态元件（SSC），用于控制致动器装置的电子控制装置（CE） 保护装置包括在电源线中并联的保险丝（F）和熔断器分流触点（FSC），以及控制致动器装置（MA，SA）的电子控制装置（CE）首先关闭并且最后断开熔断器分流触点 在电源触点或固态元件不能这样做的情况下，保险丝将会熔断以中断电源线，并且电子控制装置通过保险丝被供电以使其不能相同 保险丝熔断，使负载不能b 在故障得到纠正之前重新通电。

公开(公告)号：US20190056885A1

公开(公告)日：2019-02-21

申请号：US16160482

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06F3/06 ,  G06F12/0802 ,  G06F12/1081 ,  G06N3/04

摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

公开(公告)号：US20190042159A1

公开(公告)日：2019-02-07

申请号：US16146878

申请日：2018-09-28

申请人： Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

发明人： Ian YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin SUMBUL ,  Gregory CHEN

IPC分类号： G06F3/06 ,  H03K3/03 ,  G11C7/10

摘要： Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.

公开(公告)号：US09699096B2

公开(公告)日：2017-07-04

申请号：US14141356

申请日：2013-12-26

申请人： Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

发明人： Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

IPC分类号： H04L12/833 ,  H04L12/725 ,  H04L12/865 ,  H04L12/933 ,  H04L12/875

CPC分类号： H04L47/2458 ,  H04L45/30 ,  H04L47/56 ,  H04L47/6275 ,  H04L49/109

摘要： Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.