摘要:
A walk-in memory apparatus for an automobile seat locks the seat on a body only after the seat moves past a preset reference point when the seat, moved forwards with a seat back folded up by a seat walk-in apparatus, moves backwards with the seat back unfolded. The walk-in memory apparatus causes the entire seat to move forwards along tracks in an unlocked state when the seat back is folded up. The seat includes a track memory unit which, when the seat moves backwards with the seat back unfolded, causes the seat to be unlocked from the track when the stopper bracket is located ahead of a reference stopper and to be locked on the track when the stopper bracket is located behind the reference stopper.
摘要:
A back reclining apparatus interlocking with a seat cushion for a vehicle may include a back frame including a main frame fixed to a vehicle body and a reclining frame that may be selectively reclined around a reclining hinge on an inner surface of the main frame, a reclining locking unit connected to the main frame and the reclining frame to selectively release locking of the main frame and the reclining frame, a cushion locking unit selectively releasing locking of a cushion frame and the reclining frame, and a cushion sliding unit connected between the cushion frame and a floor panel to interlock with the reclining frame and to make the cushion frame move to slide forward when the locking of the reclining locking unit may be released and the reclining frame may be reclined around the reclining hinge.
摘要:
A back reclining apparatus interlocking with a seat cushion for a vehicle may include a back frame including a main frame fixed to a vehicle body and a reclining frame that may be selectively reclined around a reclining hinge on an inner surface of the main frame, a reclining locking unit connected to the main frame and the reclining frame to selectively release locking of the main frame and the reclining frame, a cushion locking unit selectively releasing locking of a cushion frame and the reclining frame, and a cushion sliding unit connected between the cushion frame and a floor panel to interlock with the reclining frame and to make the cushion frame move to slide forward when the locking of the reclining locking unit may be released and the reclining frame may be reclined around the reclining hinge.
摘要:
A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.
摘要:
The present invention discloses a semiconductor memory device having a plurality of banks sharing a column control unit. One column control unit is constructed to share a plurality of banks, which are adjacent with each other, thereby reducing a chip area and decreasing current consumption, and a write driver is constructed by using a cross-coupled amplifier, thereby reducing a layout area. A switching unit selectively connects a plurality of banks to a column control unit to by a control signal generated through a bank address signal and so the number of a data bus sense amplifier DBSA and a write driver WD can be reduced, thereby reducing a chip area and a current consumption. A global data bus, which is selected and then driven, and a global data bus, which is not selected and then is not driven, are equalized, as a result, there is an advantage that a current consumption is reduced in pre-charging and a pre-charge time is reduced.
摘要:
The present invention relates to an output line arrangement structure of a row decoding array used to determine a word line address of a plurality of memory cell arrays in a semiconductor memory device. The present invention can decrease an area when arranging the memory array, and can implement a high speed operation according to load reduction of a word line control signal, by arranging a part of output lines at one side end portion of a memory array, and another part thereof at the middle portion of the memory array (bit line divider), in a bus structure of word line enable and disable signals used for the row decoding array (main word line and sub-word line array constitution).