公开(公告)号：US07961837B2

公开(公告)日：2011-06-14

申请号：US12605532

申请日：2009-10-26

申请人： Jae-Boum Park ,  Young-Bo Shim

发明人： Jae-Boum Park ,  Young-Bo Shim

IPC分类号： G06M3/00

CPC分类号： H03K23/548

摘要： A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

摘要翻译： 提供响应于分配给2的倍数的数值的多个计数器使能信号的输入而输出多个控制信号的控制单元。 操作单元响应于多个控制信号的输入和递增计数信号递增或递减2的倍数。

公开(公告)号：US20100046694A1

公开(公告)日：2010-02-25

申请号：US12605532

申请日：2009-10-26

申请人： Young-Bo Shim ,  Jae-Boum Park

发明人： Young-Bo Shim ,  Jae-Boum Park

IPC分类号： G06M3/00 ,  H03K23/50

CPC分类号： H03K23/548

摘要： A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

摘要翻译： 提供响应于分配给2的倍数的数值的多个计数器使能信号的输入而输出多个控制信号的控制单元。 操作单元响应于多个控制信号的输入和递增计数信号递增或递减2的倍数。

公开(公告)号：US07609801B2

公开(公告)日：2009-10-27

申请号：US11819863

申请日：2007-06-29

申请人： Jae-Boum Park ,  Young-Bo Shim

发明人： Jae-Boum Park ,  Young-Bo Shim

IPC分类号： G06M3/00

CPC分类号： H03K23/548

摘要： A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

摘要翻译： 提供响应于分配给2的倍数的数值的多个计数器使能信号的输入而输出多个控制信号的控制单元。 操作单元响应于多个控制信号的输入和递增计数信号递增或递减2的倍数。

公开(公告)号：US20080037698A1

公开(公告)日：2008-02-14

申请号：US11819863

申请日：2007-06-29

申请人： Jae-Boum Park ,  Young-Bo Shim

发明人： Jae-Boum Park ,  Young-Bo Shim

IPC分类号： G06M3/00

CPC分类号： H03K23/548

摘要： A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

摘要翻译： 提供响应于分配给2的倍数的数值的多个计数器使能信号的输入而输出多个控制信号的控制单元。 操作单元响应于多个控制信号的输入和递增计数信号递增或递减2的倍数。

公开(公告)号：US07266033B2

公开(公告)日：2007-09-04

申请号：US11323359

申请日：2005-12-29

申请人： Young-Bo Shim

发明人： Young-Bo Shim

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C11/401 ,  G11C11/406 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A semiconductor memory device is provided. The semiconductor memory device includes: an oscillation means for generating a self-refresh enable signal and a self-refresh period pulse having a predetermined period in response to a self-refresh signal; a shift register for generating a self-refresh period level signal maintaining a different level at every self-refresh period defined by the self-refresh enable signal and the self-refresh period pulse, in response to a test mode signal; a multiplexing means for selectively outputting a data signal and the self-refresh period level signal in response to the test mode signal; and an output buffer for buffering the output signal of the multiplexing means to output the buffered signal.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括：响应于自刷新信号产生具有预定周期的自刷新使能信号和自刷新周期脉冲的振荡装置; 移位寄存器，用于响应于测试模式信号，在由自刷新使能信号和自刷新周期脉冲定义的每个自刷新周期下产生保持不同电平的自刷新周期电平信号; 多路复用装置，用于响应于测试模式信号选择性地输出数据信号和自刷新周期电平信号; 以及用于缓冲多路复用装置的输出信号以输出缓冲信号的输出缓冲器。

公开(公告)号：US06256260B1

公开(公告)日：2001-07-03

申请号：US09570729

申请日：2000-05-12

申请人： Young-Bo Shim ,  Woo-Soon Kang

发明人： Young-Bo Shim ,  Woo-Soon Kang

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/225 ,  G11C8/06 ,  G11C11/4093

摘要： A synchronous semiconductor memory device having a plurality of external signal input buffer and a plurality of latch circuits, includes: a clock buffer for receiving an external clock signal to generate a buffered clock signal; a chip select buffer for receiving an external chip select signal and the buffered clock signal from said clock buffer to generate a buffered chip select signal, an inverted buffered chip select signal and a latch control signal, wherein the latch control signal is activated when the external clock signal is at the rising edge and the external chip select signal is low; a plurality of external signal buffers for receiving external signals to generate buffered signals and inverted buffered signals; and a plurality of latch circuits for latching and outputting the buffered signals and the inverted buffer signals to an internal logic circuit in response to the latch control signal.

摘要翻译： 一种具有多个外部信号输入缓冲器和多个锁存电路的同步半导体存储器件，包括：时钟缓冲器，用于接收外部时钟信号以产生缓冲的时钟信号; 芯片选择缓冲器，用于接收来自所述时钟缓冲器的外部芯片选择信号和缓冲的时钟信号，以产生缓冲芯片选择信号，反相缓冲芯片选择信号和锁存控制信号，其中当外部 时钟信号处于上升沿，外部芯片选择信号为低电平; 多个外部信号缓冲器，用于接收外部信号以产生缓冲信号和反相缓冲信号; 以及多个锁存电路，用于响应于锁存控制信号而将缓冲信号和反相缓冲器信号锁存并输出到内部逻辑电路。

公开(公告)号：US06965532B2

公开(公告)日：2005-11-15

申请号：US10744320

申请日：2003-12-22

申请人： Young-Bo Shim

发明人： Young-Bo Shim

IPC分类号： G11C11/40 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066

摘要： A data output control apparatus and method of a semiconductor memory device exactly synchronize the first read data with a clock signal by solving a problem that the first read data is faster than the clock signal as much as a transit time from a voltage level Vddq/2 to a power voltage Vddq or a ground voltage Vssq. For the purpose, the apparatus for sequentially outputting a plurality of read data stored in the semiconductor memory device includes a first path through which a first read data output control signal for controlling the output of the first read data among the plurality of read data is passing, and a second path through which a second data output control signal for controlling the output of the other read data following the first read data among the plurality of read data is passing, wherein the first read data output control signal is delayed as much as the transit time and outputted through the first path in response to a preamble time control signal for reporting the start of a data read operation.

摘要翻译： 半导体存储器件的数据输出控制装置和方法通过解决第一读取数据比时钟信号更快的问题，将第一读取数据与时钟信号精确地同步，并且从电压电平Vddq / 2 电压Vddq或接地电压Vssq。 为此，用于顺序地输出存储在半导体存储器件中的多个读取数据的装置包括第一路径，用于控制多个读取数据中的第一读取数据的输出的第一读取数据输出控制信号通过该第一路径通过 以及第二路径，用于控制多个读取数据之后的第一读取数据之后的其他读取数据的输出的第二数据输出控制信号通过，其中第一读取数据输出控制信号被延迟至 响应于用于报告数据读取操作的开始的前导码时间控制信号，通过第一路径输出。

公开(公告)号：US06181623B2

公开(公告)日：2001-01-30

申请号：US09472984

申请日：1999-12-28

申请人： Young-Bo Shim ,  Yung-Jin Gang

发明人： Young-Bo Shim ,  Yung-Jin Gang

IPC分类号： G11C702

CPC分类号： H01L27/10897 ,  G11C7/065 ,  H01L29/7302

摘要： In semiconductor memory device including a sense amplifier, the sense amplifier includes a bit line and a bit line bar coupled to the memory cell, a data line and an inverting data lines for transferring an output of the sense amplifier, a first P-type MOS/BIPOLAR composite transistor having a source/emitter coupled to a first level potential, a gate/base coupled to the inverting data line and a drain/collector coupled to the data line, a second P-type MOS/BIPOLAR composite transistor having a source/emitter coupled to the first level potential, a gate/base coupled to the data line and a drain/collector coupled to the inverting data line, a first N-type MOS/BIPOLAR composite transistor having a drain/collector coupled to the data line and a gate/base coupled to the inverting data line, a second N-type MOS/BIPOLAR composite transistor having a drain/collector coupled to the inverting data line and a gate/base coupled to the data line, a first load coupled between a source/emitter of the first N-type MOS/BIPOLAR composite transistor and a second level potential, and a second load coupled between a source/emitter of the second N-type MOS/BIPOLAR composite transistor and the second level potential.

摘要翻译： 在包括读出放大器的半导体存储器件中，读出放大器包括耦合到存储单元的位线和位线条，用于传送读出放大器的输出的数据线和反相数据线，第一P型MOS / BIPOLAR复合晶体管，其具有耦合到第一电平电位的源极/发射极，耦合到反相数据线的栅极/基极和耦合到数据线的漏极/集电极，具有源极的第二P型MOS /双极复合晶体管 /发射极耦合到第一电平电位，耦合到数据线的栅极/基极和耦合到反相数据线的漏极/集电极，具有耦合到数据线的漏极/集电极的第一N型MOS /双极复合晶体管 以及耦合到所述反相数据线的栅极/基极，具有耦合到所述反相数据线的漏极/集电极和耦合到所述数据线的栅极/基极的第二N型MOS /双极复合晶体管，耦合在所述反相数据线之间的第一负载 源/发射器 第一N型MOS / BIPOLAR复合晶体管和第二电平电位，以及耦合在第二N型MOS / BIPOLAR复合晶体管的源极/发射极与第二电平电位之间的第二负载。

公开(公告)号：US08284615B2

公开(公告)日：2012-10-09

申请号：US12979678

申请日：2010-12-28

申请人： Young-Bo Shim

发明人： Young-Bo Shim

IPC分类号： G11C11/34

CPC分类号： G11C11/40611 ,  G11C7/04 ,  G11C8/12 ,  G11C8/18 ,  G11C11/40615

摘要： A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal having refresh mode information, a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to an active signal enabled in an active mode, and a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array.

摘要翻译： 用于半导体存储器件的刷新控制电路包括：刷新控制器，被配置为响应于指示刷新模式的开始的刷新模式进入信号，控制刷新信号在一个刷新周期期间使能的次数;以及模式确定 具有刷新模式信息的信号;刷新计数器，配置为响应于在活动模式中启用的活动信号计数刷新信号而输出用于刷新操作的行地址;以及行地址解码器，被配置为对行地址进行解码以生成 行地址选择信号，用于顺序访问单元阵列内的字线。

公开(公告)号：US08284614B2

公开(公告)日：2012-10-09

申请号：US12979642

申请日：2010-12-28

申请人： Young-Bo Shim

发明人： Young-Bo Shim

IPC分类号： G11C11/34

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C29/12015 ,  G11C29/50016

摘要： A semiconductor memory device includes a refresh counter for counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode, an external address input buffer for buffering an external address to output an internal address in response to a mode selection signal enabled in an external address refresh mode, an address selector for outputting the refresh address from the refresh counter as a selection row address in a normal refresh mode and outputting the internal address from the external address input buffer as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal, and a row address decoder for generating a row address selection signal for sequentially accessing word lines by decoding the selection row address.

摘要翻译： 半导体存储器件包括：刷新计数器，用于响应于在激活模式下使能的有源模式信号输出刷新信号并输出​​刷新地址;外部地址输入缓冲器，用于缓冲外部地址以响应于一个内部地址输出内部地址 模式选择信号在外部地址刷新模式下被使能，地址选择器用于在正常刷新模式下从刷新计数器输出刷新地址作为选择行地址，并将来自外部地址输入缓冲器的内部地址作为选择行地址输出 响应于刷新信号和模式选择信号的外部地址刷新模式，以及行地址解码器，用于通过解码选择行地址来产生用于顺序访问字线的行地址选择信号。