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29 条记录 (耗时 0.016 秒)

    Solid-state image pickup device and camera system
    1.
    发明授权
    Solid-state image pickup device and camera system 有权
    固态图像拾取装置和相机系统

    公开(公告)号：US08890990B2

    公开(公告)日：2014-11-18

    申请号：US13237366

    申请日：2011-09-20

    申请人： Yasuaki Hisamatsu

    发明人： Yasuaki Hisamatsu

    IPC分类号： H04N3/14 ,  H04N5/378 ,  H03M1/12 ,  H03K23/54 ,  H04N5/357 ,  H04N5/376 ,  H03M1/56

    CPC分类号： H04N5/378 ,  H03K23/548 ,  H03M1/123 ,  H03M1/56 ,  H04N5/357 ,  H04N5/3765

    摘要： A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line.

    摘要翻译： 一种固态图像拾取装置和照相机系统，其中：（1）计数器以列为单位组织成计数器组和存储器组; （2）每个列中的各个计数器级联连接在各个位之间; （3）开关设在各个计数器的位输出部分; （4）各个开关的连接侧通常连接到列信号传输线，并且开关的输出侧与其他单独的位共享; （5）存储用于水平传送的数字数据的存储器（锁存电路）的输入共享列信号传送线; 和（6）对应于各个位的存储器的输出通过开关连接到布线以与列信号传输线正交的数据传输信号线。

    Counter circuit and method of operating the same
    2.
    发明授权
    Counter circuit and method of operating the same 失效
    计数器电路及其操作方法

    公开(公告)号：US07609801B2

    公开(公告)日：2009-10-27

    申请号：US11819863

    申请日：2007-06-29

    申请人： Jae-Boum Park ,  Young-Bo Shim

    发明人： Jae-Boum Park ,  Young-Bo Shim

    IPC分类号： G06M3/00

    CPC分类号： H03K23/548

    摘要： A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

    摘要翻译： 提供响应于分配给2的倍数的数值的多个计数器使能信号的输入而输出多个控制信号的控制单元。 操作单元响应于多个控制信号的输入和递增计数信号递增或递减2的倍数。

    High-speed synchronous counters with reduced logic complexity
    3.
    发明授权
    High-speed synchronous counters with reduced logic complexity 有权
    具有降低逻辑复杂度的高速同步计数器

    公开(公告)号：US06826249B1

    公开(公告)日：2004-11-30

    申请号：US10268481

    申请日：2002-10-10

    申请人： Ahmed Younis

    发明人： Ahmed Younis

    IPC分类号： G06M300

    CPC分类号： H03K23/54 ,  H03K23/548 ,  H03K23/588

    摘要： Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

    摘要翻译： 描述了具有减少的组合逻辑的快速同步计数器。 在一个实施例中，四位移位寄存器被配置在环中并且用数据模式预设（例如，1000）。 然后，寄存器迅速转换成四个独特状态中的任何一个。 连接到移位寄存器的组合逻辑将四个唯一状态转换成代表四个状态的二位二进制信号。 在一般情况下，根据本实施例的计数器表示使用2N个同步存储元件的N位二进制数。 可以组合两个或更多计数器来产生较大的同步计数器。 根据另一实施例的升/减计数器连接到多路径延迟线以创建可变延迟电路。 延迟电路的切换速度与延迟设置的数量无关。 还有利的是，随着延迟粒度的变化，延迟电路在功耗和面积方面线性缩放。

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
    半导体器件和电子器件

    公开(公告)号：US20110176652A1

    公开(公告)日：2011-07-21

    申请号：US12984061

    申请日：2011-01-04

    申请人： Yoshiyuki KUROKAWA

    发明人： Yoshiyuki KUROKAWA

    IPC分类号： H03K21/00

    CPC分类号： H03K23/548 ,  H01L27/14609 ,  H01L27/14665 ,  H03M1/123 ,  H03M1/60 ,  H04N5/357 ,  H04N5/374 ,  H04N5/378

    摘要： Noise in a semiconductor device including a photo sensor is reduced. The semiconductor device includes an analog/digital converter and a photo sensor including a photodiode. The analog/digital converter includes an oscillation circuit and a counter circuit. A first signal output from the photo sensor is input to the oscillation circuit. The oscillation circuit has a function of outputting a second signal obtained by a change in oscillation frequency of the first signal. The counter circuit has a count function by which addition or subtraction is performed by a control signal with the second signal used as a clock signal. The counter circuit performs subtraction during the reset operation of the photo sensor. The counter circuit performs addition during the selection operation of the photo sensor. Thus, the output value of the analog/digital converter can be corrected.

    摘要翻译： 包括光传感器的半导体器件的噪声减小。 半导体器件包括模拟/数字转换器和包括光电二极管的光电传感器。 模拟/数字转换器包括振荡电路和计数器电路。 从光传感器输出的第一信号被输入到振荡电路。 振荡电路具有输出通过第一信号的振荡频率的变化而获得的第二信号的功能。 计数器电路具有通过控制信号执行加法或减法的计数功能，第二信号用作时钟信号。 计数器电路在光传感器的复位操作期间进行减法。 计数器电路在光传感器的选择操作期间执行相加。 因此，可以校正模拟/数字转换器的输出值。

    Counter circuit and method of operating the same
    8.
    发明申请
    Counter circuit and method of operating the same 失效
    计数器电路及其操作方法

    公开(公告)号：US20080037698A1

    公开(公告)日：2008-02-14

    申请号：US11819863

    申请日：2007-06-29

    申请人： Jae-Boum Park ,  Young-Bo Shim

    发明人： Jae-Boum Park ,  Young-Bo Shim

    IPC分类号： G06M3/00

    CPC分类号： H03K23/548

    摘要： A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

    摘要翻译： 提供响应于分配给2的倍数的数值的多个计数器使能信号的输入而输出多个控制信号的控制单元。 操作单元响应于多个控制信号的输入和递增计数信号递增或递减2的倍数。

    ASYNCHRONOUS LOADABLE DOWN COUNTER
    10.
    发明申请
    ASYNCHRONOUS LOADABLE DOWN COUNTER 有权
    异步负载下降计数器

    公开(公告)号：US20110243295A1

    公开(公告)日：2011-10-06

    申请号：US12752891

    申请日：2010-04-01

    申请人： Josephus C. Ebergen ,  Adam Megacz

    发明人： Josephus C. Ebergen ,  Adam Megacz

    IPC分类号： H03K21/00

    CPC分类号： H03K23/548 ,  H03K21/38

    摘要： The disclosed embodiments relate to an asynchronous down counter, which can be loaded with any value N and then decrement exactly N times. The counter comprises an array of cells, wherein each cell is configured to hold a digit in a redundant base-k representation of a number contained in the array of cells. Each cell further comprises a finite state machine that defines state transitions between states, where these states are held on wires and state transitions are synchronized between neighboring cells. Each cell is further configured to asynchronously borrow, if possible, from a more significant adjacent cell to increase a value of a digit in the cell. This asynchronous borrowing improves performance by ensuring that a decrement operation, which decrements a digit in a least significant cell in the array, will borrow from an adjacent more significant cell, without having to wait for the completion of a rippling sequence of borrows from more significant cells.

    摘要翻译： 所公开的实施例涉及异步向下计数器，其可以被加载任何值N，然后精确地递减N次。 该计数器包括一个单元阵列，其中每个单元被配置成将数字保存在包含在单元阵列中的数字的冗余base-k表示中。 每个单元还包括有限状态机，其定义状态之间的状态转换，其中这些状态保持在导线上，状态转换在相邻单元之间同步。 每个单元还被配置为如果可能，从更重要的相邻单元异步地借用以增加单元中的数字的值。 这种异步借用通过确保减少数组中最不重要的单元格中的数字的递减操作将从相邻的更重要的单元借位，而不必等待从更显着的方式完成借款的波动序列，从而提高性能 细胞。