公开(公告)号：US20130140516A1

公开(公告)日：2013-06-06

申请号：US13599259

申请日：2012-08-30

Applicant: Hyun-Ju LEE ,  Jae-Kyu LEE

Inventor： Hyun-Ju LEE ,  Jae-Kyu LEE

IPC: H01L47/00 ,  H01L21/02

CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.

Abstract translation: 电阻式存储器件可以包括衬底，栅电极结构，第一杂质区，第二杂质区，第一金属硅化物图案和第二金属硅化物图案。 衬底可以具有其中隔离图案和第一有源图案可以沿第一方向交替布置的第一区域，以及可以在第一方向上延伸线性第二有源图案的第二区域。 栅极电极结构可以布置在衬底的第一区域和第二区域之间。 第一和第二杂质区可以形成在第一和第二杂质区中。 第一金属硅化物图案可以具有被配置为与第一杂质区域的上表面接触的隔离形状。 第二金属硅化物图案可以与第二杂质区域的上表面接触。

公开(公告)号：US20170170234A1

公开(公告)日：2017-06-15

申请号：US15234257

申请日：2016-08-11

Applicant: Jae-Kyu LEE ,  Sung-In KIM ,  Ki-Seok SUH

Inventor： Jae-Kyu LEE ,  Sung-In KIM ,  Ki-Seok SUH

IPC: H01L27/22 ,  H01L43/12

CPC classification number: H01L27/228 ,  G11C11/1655 ,  G11C11/1659

Abstract: A magnetoresistive random access memory (MRAM) device including a substrate including a plurality of active patterns arranged along a first direction, each of the active patterns extending in a diagonal direction with respect to the first direction; a plurality of gate structures on the substrate, the gate structures extending in a second direction substantially perpendicular to the first direction; a source line structure electrically connected to source regions of the respective active patterns, the source line structure extending in the first direction; a plurality of magnetic tunnel junction (MTJ) structures electrically connected to drain regions of the respective active patterns, the MTJ structures being spaced apart from each other; and a bit line structure electrically connected to the MTJ structures in respective memory cells, the memory cells sharing with the source line structure.

公开(公告)号：US20090009407A1

公开(公告)日：2009-01-08

申请号：US12136929

申请日：2008-06-11

Applicant: Suk-Chan HONG ,  Jae-Kyu LEE ,  Jun-Chul KANG

Inventor： Suk-Chan HONG ,  Jae-Kyu LEE ,  Jun-Chul KANG

IPC: H01Q1/24

CPC classification number: H01Q1/243 ,  H01Q5/40 ,  H01Q9/0421 ,  H01Q9/42 ,  H01Q21/30

Abstract: A mobile phone includes a multi-band antenna which is mutually connected in a dependent manner for operation according to a signal transmitted to and received from the mobile phone; and a resonance unit for generating resonance for multiple frequency bands as ends of the multi-band antenna are spaced apart at a predetermined interval, to improve mute performance, reduce SAR, and prevent a reduction in call performance due to an influence of a user's body and hand when holding the mobile phone to make a call.

Abstract translation: 移动电话包括：多频带天线，其以依赖方式相互连接，用于根据发送给移动电话并从移动电话接收的信号进行操作; 并且用于产生作为多频带天线的端部的多个频带的谐振的谐振单元以预定间隔隔开，以改善静音性能，降低SAR，并且防止由于用户身体的影响而引起的呼叫性能的降低 手持手机拨打电话。

公开(公告)号：US20060211197A1

公开(公告)日：2006-09-21

申请号：US11381517

申请日：2006-05-03

Applicant: Jae-Kyu LEE

Inventor： Jae-Kyu LEE

IPC: H01L21/8242 ,  H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/41775 ,  H01L29/41783 ,  Y10S257/90

Abstract: In a MOS transistor and a method of manufacturing the same, a gate structure including a gate insulating layer and a gate electrode is formed on a semiconductor substrate. A first insulating layer is formed to cover the gate structure. A second insulating layer is formed on the substrate that is spaced apart from the first insulating layer. A lightly doped source/drain region is formed in the surface portions of the substrate between the second insulating layer and the gate structure. A source/drain extension layer are formed on the lightly doped source/drain region. A heavily doped source/drain region is formed on the second insulating layer so as to connect with the source/drain extension layer. The short channel effect is suppressed and the source/drain junction capacitance is reduced.

Abstract translation: 在MOS晶体管及其制造方法中，在半导体衬底上形成包括栅极绝缘层和栅电极的栅极结构。 形成第一绝缘层以覆盖栅极结构。 在与第一绝缘层间隔开的基板上形成第二绝缘层。 在第二绝缘层和栅极结构之间的衬底的表面部分中形成轻掺杂源/漏区。 源极/漏极延伸层形成在轻掺杂的源极/漏极区域上。 在第二绝缘层上形成重掺杂的源极/漏极区，以便与源极/漏极延伸层连接。 短沟道效应被抑制，源/漏结电容减小。