公开(公告)号：US20150014775A1

公开(公告)日：2015-01-15

申请号：US14273789

申请日：2014-05-09

申请人： Jae-Woo SEO ,  Gun-Ok JUNG ,  Min-Su KIM ,  Sang-Shin HAN ,  Ju-Hyun KANG ,  Uk-Rae CHO

发明人： Jae-Woo SEO ,  Gun-Ok JUNG ,  Min-Su KIM ,  Sang-Shin HAN ,  Ju-Hyun KANG ,  Uk-Rae CHO

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L23/538 ,  H01L27/092

CPC分类号： H01L29/785 ,  H01L23/5286 ,  H01L23/538 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括：第一源电极，被配置为将第一电力轨连接到第一杂质区，第一电源轨耦合到第一电压源;第二源极，被配置为将第二电力轨连接到第二杂质区; 第二电源轨耦合到第二电压源，第一和第二电压源不同，第一和第二杂质区上的栅电极，第一杂质区上的第一漏电极，第二杂质区上的第二漏电极， 连接到所述第一漏电极和所述第二漏极的互连线，所述互连线形成至少一个闭环。

公开(公告)号：US20160300840A1

公开(公告)日：2016-10-13

申请号：US15094280

申请日：2016-04-08

申请人： Jae-Woo SEO ,  Jaeha LEE

发明人： Jae-Woo SEO ,  Jaeha LEE

IPC分类号： H01L27/092 ,  G06F17/50 ,  H01L23/528 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/768

CPC分类号： G06F17/5077 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207

摘要： A method for manufacturing a semiconductor device is provided. The method includes disposing pre-conductive lines and post-conductive lines for forming first and second cells. The first and second cells are adjacent to each other in a first direction. A first conductive line of the first cell extends in a second direction perpendicular to the first direction and is adjacent to a boundary between the first and second cells. A second conductive line and a third conductive line of the second cell extend in the first direction and are adjacent to the boundary. The second and third conductive lines are respectively disposed on two non-adjacent tracks, among a plurality of tracks that extend in the first direction. The first conductive line intersects one of the two non-adjacent tracks and one track disposed between the two non-adjacent tracks.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括布置用于形成第一和第二单元的预导线和导电线。 第一和第二单元在第一方向上彼此相邻。 第一单元的第一导电线在垂直于第一方向的第二方向上延伸并且与第一和第二单元之间的边界相邻。 第二单元的第二导线和第三导线在第一方向上延伸并且与边界相邻。 第二和第三导线分别设置在沿着第一方向延伸的多个轨道中的两个不相邻的轨道上。 第一导线与两个不相邻的轨道中的一个相交，一个轨道设置在两个不相邻的轨道之间。

公开(公告)号：US20160300766A1

公开(公告)日：2016-10-13

申请号：US15094764

申请日：2016-04-08

申请人： Ha-Young KIM ,  JinTae KIM ,  Jae-Woo SEO ,  Dong-yeon HEO

发明人： Ha-Young KIM ,  JinTae KIM ,  Jae-Woo SEO ,  Dong-yeon HEO

IPC分类号： H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L21/823475 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0629

摘要： A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.

摘要翻译： 一种制造半导体器件的方法包括提供用于形成彼此相邻的第一逻辑单元和第二逻辑单元的预导线和后导线，以及相邻的虚拟单元和第三逻辑单元 对彼此。 与第二逻辑单元相邻的第一导线从第一逻辑单元的导线之间隔开第二参考距离，与第二逻辑单元相邻的第二导线相隔离第二逻辑单元的导线之间 。 与第三逻辑单元相邻的虚拟线从虚拟单元的导线之间隔开第二基准距离，该第二基准距离与第三逻辑导线之间的与虚设单元相邻的第三导线 细胞。 第二参考距离大于第一参考距离。