公开(公告)号：US06654869B1

公开(公告)日：2003-11-25

申请号：US09428399

申请日：1999-10-28

申请人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore

IPC分类号： G06F500

CPC分类号： G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

摘要翻译： 微处理器包括提取单元，指令分解单元以及调度和完成控制逻辑。 提取单元从指令高速缓存中检索一组指令。 指令解码单元接收所提取的指令集，并将该组指令组织到指令组中。 调度和完成逻辑将组标签分配给指令组，并将组标记记录在完成表的条目中，以跟踪包括指令组的指令的完成状态。 调度和控制逻辑可以在对应于每个指令组的完成表条目中记录单个指令地址。 优选地，单指令地址是指令组中的第一指令的指令地址。 响应于检测到指令组中的指令产生的异常，处理器可以刷新指令组。

公开(公告)号：US06658555B1

公开(公告)日：2003-12-02

申请号：US09435077

申请日：1999-11-04

申请人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F930

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3885

摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

公开(公告)号：US06662294B1

公开(公告)日：2003-12-09

申请号：US09671868

申请日：2000-09-28

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F938

CPC分类号： G06F9/30072 ,  G06F9/30174

摘要： A microprocessor and method of processing instructions therein are disclosed. Initially, a sequence of instructions is dispatched by a dispatch unit of the microprocessor. A code sequence recognition unit (CSR) is configured to detect a short branch sequence within the sequence of instruction, where the short branch sequence includes a condition setting instruction, a conditional branch, and at least one additional instruction that is executed if the conditional branch is not taken. The short branch sequence is then internally converted to a predicated instruction sequence that includes the condition setting instruction and a predicated instruction corresponding to each additional instruction in the short branch sequence. The predicated instruction sequence is then executed in at least one functional unit of the processor. Detecting the short branch sequence may include calculating the relative branch address associated with the conditional branch instruction and comparing the relative branch address to a specified maximum. In one embodiment, the received sequence of instructions may be converted into an instruction group by the processor. In this embodiment, the specified maximum number of instructions in a short branch sequence may be a function of the number of instructions in an instruction group. In an embodiment where the conditional branch statement is preferably allocated to the last slot of the instruction group, the additional instructions in the short branch sequence are located in the next subsequent instruction group. Converting the short branch sequence to the predicated instruction sequence may include converting each additional instruction in the short branch sequence to an analogous predicated instruction. In one embodiment, converting each additional instruction to its analogous predicated instruction includes determining a predicated instruction opcode for each additional instruction in the short branch sequence by adjusting the opcode of each additional instruction by a predetermined offset. In another embodiment, the opcode conversion may be accomplished with an opcode lookup table.

公开(公告)号：US06609190B1

公开(公告)日：2003-08-19

申请号：US09478311

申请日：2000-01-06

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F930

CPC分类号： G06F9/3865 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857

摘要： A processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currently eligible to issue for execution. The instruction is stored in the secondary issue queue if the instruction is currently ineligible to issue for execution. An instruction may be moved from the primary issue queue to the secondary issue queue if instruction is dependent upon results from another instruction. In one embodiment, the instruction may be moved from the primary issue queue to the secondary issue queue after issuing the instruction for execution. In this embodiment, the instruction may be maintained in the secondary issue queue for a specified duration. Thereafter, the secondary issue queue entry containing the instruction is deallocated if the instruction has not been rejected.

摘要翻译： 一种处理器和数据处理系统，适用于向发布单元发送指令。 问题单元包括主要问题队列和次要问题队列。 如果指令当前有资格发行执行，指令将存储在主要问题队列中。 如果该指令当前不符合要发行执行的规定，则该指令存储在辅助发行队列中。 如果指令取决于另一个指令的结果，则指令可以从主要问题队列移动到次要发布队列。 在一个实施例中，在发出用于执行的指令之后，指令可以从主要问题队列移动到次要发布队列。 在该实施例中，可以在指定持续时间内将指令维持在次要发行队列中。 此后，如果指令未被拒绝，则包含指令的次要发行队列条目被解除分配。

公开(公告)号：US06725354B1

公开(公告)日：2004-04-20

申请号：US09594631

申请日：2000-06-15

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F900

CPC分类号： G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3879 ,  G06F9/3885 ,  G06F15/7832

摘要： A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions.

摘要翻译： 微处理器包括第一处理器核和第二处理器核。 第一核心包括第一处理块。 第一处理块包括适于执行第一类型的指令的执行单元。 第二核心包括第二处理块。 第二处理块包括执行单元，如果指令是第一类型，则适合于执行指令。 处理器还包括共享执行单元。 如果指令是第二类型，则第一和第二处理器核心适于将指令转发到共享执行单元以执行。 在一个实施例中，第一类型的指令包括固定点指令，加载/存储指令和分支指令，并且第二类型的指令包括浮点指令。

公开(公告)号：US06766442B1

公开(公告)日：2004-07-20

申请号：US09538992

申请日：2000-03-30

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F900

CPC分类号： G06F9/3804 ,  G06F9/30094 ,  G06F9/383 ,  G06F9/3846 ,  G06F9/3848

摘要： A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions, a condition register, and a branch prediction circuit that predicts a condition register-dependent branch instruction by reference to a potentially stale condition register value to produce a speculative instruction fetch address. In a preferred embodiment, the processor includes branch execution circuitry that subsequently determines if the speculative instruction fetch address is correct by reference to a non-stale value of the condition register.

摘要翻译： 具有改进的分支预测精度的处理器包括执行顺序指令的至少一个执行单元，条件寄存器和分支预测电路，其通过参考潜在的陈旧条件寄存器值来预测与条件寄存器相关的分支指令，以产生推测指令 取地址。 在优选实施例中，处理器包括分支执行电路，其随后通过参考条件寄存器的非陈旧值确定推测指令提取地址是否正确。

公开(公告)号：US06728866B1

公开(公告)日：2004-04-27

申请号：US09652049

申请日：2000-08-31

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F930

CPC分类号： G06F9/384 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/3891

摘要： A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are received. Dependency logic determines if any dependencies between the first and second instructions. The dependency logic then selects between first and second issue queue partitions for storing the first and second instructions pending issue based upon the dependency determination, wherein the first issue queue partition issues instructions to a first execution unit and the second issue queue partition issues instructions to a second execution unit. The first and second issue queue partitions may be asymmetric with respect to a first register file in which instruction results are stored. The first and second instructions are then stored in the selected partitions. Selecting between the first and second issue queue partitions may include selecting a common issue queue partition for the first and second instructions if there is a dependency between the first and second instructions and selecting between the first and second issue queue partition may be based upon a fairness algorithm if the first and second instructions lack dependencies.

摘要翻译： 公开了一种用于处理定时比较的处理指令的微处理器和方法。 接收包括第一指令和第二指令的指令序列。 依赖逻辑确定第一和第二条指令之间是否有依赖关系。 所述依赖性逻辑然后在第一和第二发布队列分区之间选择用于基于所述依赖性确定存储所述第一和第二指令等待发布，其中所述第一问题队列分区向第一执行单元发出指令，并且所述第二发布队列分区向 第二执行单元。 相对于其中存储指令结果的第一寄存器文件，第一和第二问题队列分区可以是不对称的。 然后将第一和第二指令存储在所选择的分区中。 在第一和第二发布队列分区之间的选择可以包括为第一和第二指令选择共同的问题队列分区，如果在第一和第二指令之间存在依赖关系，并且在第一和第二发布队列之间的选择可以基于公平性 算法如果第一个和第二个指令缺乏依赖关系。

公开(公告)号：US06678820B1

公开(公告)日：2004-01-13

申请号：US09538993

申请日：2000-03-30

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F900

CPC分类号： G06F9/30181 ,  G06F9/3848

摘要： A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions and a plurality of branch prediction circuits including a lock acquisition branch prediction circuit that predicts a speculative execution path for a conditional branch instruction. The processor further includes a selector that selects the speculative execution path predicted by the lock acquisition branch prediction circuit in response to an indication that the conditional branch instruction is dependent upon lock acquisition. In a preferred embodiment, the indication that the conditional branch instruction is dependent upon lock acquisition is encoded within the conditional branch instruction.

摘要翻译： 具有改进的分支预测精度的处理器包括执行顺序指令的至少一个执行单元和包括锁定获取分支预测电路的多个分支预测电路，该预测电路预测条件转移指令的推测执行路径。 处理器还包括选择器，其响应于条件分支指令取决于锁获取的指示，选择由锁获取分支预测电路预测的推测执行路径。 在优选实施例中，条件分支指令依赖于锁获取的指示被编码在条件分支指令内。

公开(公告)号：US06658558B1

公开(公告)日：2003-12-02

申请号：US09538991

申请日：2000-03-30

申请人： James Allan Kahle ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Charles Roberts Moore

IPC分类号： G06F938

CPC分类号： G06F9/3861 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3806 ,  G06F9/3846 ,  G06F9/3848

摘要： A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions and branch processing circuitry that processes branch instructions. The branch processing circuitry includes a number of branch prediction circuits that are each capable of providing a branch prediction for a conditional branch instruction and a selector that selects a branch prediction of a branch prediction circuit based upon the type of condition upon which the conditional branch instruction depends. The selector preferably includes hardware that determines the type of condition upon which the conditional branch instruction depends by reference to an instruction context defined by one or more instructions adjacent the conditional branch instruction in programmed sequence. The branch processing circuitry further includes path address logic that determines a path address of the selected branch prediction. Thus, branch prediction accuracy can be improved by considering the type of condition upon which a conditional branch instruction depends, rather than just branch history.

摘要翻译： 具有改进的分支预测精度的处理器包括执行顺序指令的至少一个执行单元和处理分支指令的分支处理电路。 分支处理电路包括多个分支预测电路，每个分支预测电路能够为条件分支指令提供分支预测，以及选择器，其基于条件分支指令的条件类型来选择分支预测电路的分支预测 依靠。 选择器优选地包括硬件，硬件通过参考由编程序列中的与条件分支指令相邻的一个或多个指令定义的指令上下文来确定条件转移指令所依赖的条件类型。 分支处理电路还包括确定所选分支预测的路径地址的路径地址逻辑。 因此，通过考虑条件分支指令所依赖的条件的类型而不仅仅是分支历史，可以提高分支预测精度。

公开(公告)号：US5692218A

公开(公告)日：1997-11-25

申请号：US639274

申请日：1996-04-25

申请人： Michael Scott Allen ,  Michael Julio Garcia ,  Charles Roberts Moore ,  Robert James Reese

发明人： Michael Scott Allen ,  Michael Julio Garcia ,  Charles Roberts Moore ,  Robert James Reese

IPC分类号： G06F13/16 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4217

摘要： A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, an operation request package is transmitted to a second device from a first device, which informs the second device of the total amount of data to be transferred. A transfer signal is then transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device. A second address package, comprising a byte count and an address, are transmitted to the second device from the first device on the address bus. If data is to be transferred, the data is then transferred on the data bus. Finally, a reply signal may be transmitted between the first and second devices, acknowledging the success or failure of the data transfer.

摘要翻译： 一种用于在数据处理系统内将数据从第一设备传送到第二设备的数据处理系统中的方法和系统。 数据处理系统包括数据总线，地址总线，与存储器相关联的第一地址空间和与输入/输出设备相关联的第二地址空间。 最初，操作请求包从第一设备发送到第二设备，第一设备通知第二设备要传送的总数据量。 然后在数据处理系统中传送传送信号。 传送信号将传送标识为关于与输入/输出设备相关联的第二地址空间中的地址的传送。 然后，第一地址包从地址总线上的第一设备发送到第二设备。 第一地址包包括传送标识符，与第一设备相关联的第一标识符和与第二设备相关联的第二标识符。 包括字节计数和地址的第二地址包从地址总线上的第一设备发送到第二设备。 如果要传输数据，则数据在数据总线上传输。 最后，可以在第一和第二设备之间传送应答信号，确认数据传输的成功或失败。