公开(公告)号：US06658555B1

公开(公告)日：2003-12-02

申请号：US09435077

申请日：1999-11-04

申请人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F930

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3885

摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

公开(公告)号：US06543002B1

公开(公告)日：2003-04-01

申请号：US09435066

申请日：1999-11-04

申请人： James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F1100

CPC分类号： G06F11/0721 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/0793 ,  G06F11/1405

摘要： A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch. The hang recovery unit then asserts a force reject signal to an execution unit to reject all instructions pending in the execution unit's pipeline and a flush signal to the execution unit that results in the processor flushing a set of instructions. The hang recovery unit then negates the force reject, stop completion, and stop dispatch signals to resume processor operation. In one embodiment, the recovery sequence includes entering a relaxed execution mode, such as a debug mode, a serial operation mode, or an in-order mode prior to resuming processor operation. In one embodiment, the processor advances a completion tag upon completing an instruction. In this manner the completion tag indicates the instruction that is next to complete. In one embodiment, the hang recovery sequence includes flushing the processor of an instruction set comprising all instructions with tag information greater than the completion tag. In another embodiment, all instructions with tag information greater than or equal to the completion tag are flushed.

公开(公告)号：US06298436B1

公开(公告)日：2001-10-02

申请号：US09327644

申请日：1999-06-08

申请人： James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

发明人： James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

IPC分类号： G06F9305

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3842

摘要： A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order. The first reservation instruction is speculatively executed by placing a reservation for a particular data address of the first reservation instruction, in response to completion of instructions queued for the execution unit which occur prior to the first reservation instruction in the program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.

摘要翻译： 一种用于处理器系统中的原子存储器访问的方法和系统，其中所述处理器系统能够相对于特定程序顺序发出并执行不正常的多个指令。 推测性地向处理器系统的执行单元发出第一预约指令。 在发行时，响应于在程序中的第一预约指令之后发生的执行单元中检测到任何先前执行的预定指令而从执行单元中刷新在程序顺序中的第一预约指令之后发生的执行单元排队的指令 订购。 响应于在程序顺序中的第一预约指令之前发生的执行单元排队的指令的完成，通过对第一预约指令的特定数据地址进行预约来推测地执行第一预约指令，使得预约指令 相对于合作条件存储指令，以任何顺序被推测地发行和执行的这些被按顺序执行。

公开(公告)号：US06336183B1

公开(公告)日：2002-01-01

申请号：US09259140

申请日：1999-02-26

申请人： Hung Qui Le ,  Robert Greg McDonald ,  David James Shippy ,  Larry Edward Thatcher

发明人： Hung Qui Le ,  Robert Greg McDonald ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F9312

CPC分类号： G06F9/3889 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

摘要： In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

摘要翻译： 在处理器中，存储指令被划分或破解为存储数据，并且存储地址生成部分用于在两个执行单元内进行单独和并行执行。 存储指令的地址生成部分在加载存储单元内执行，而指令的存储数据部分在除加载存储单元之外的执行单元中执行。 如果存储指令是固定点执行单元，则在固定点单元内执行存储数据部分。 如果存储指令是浮点存储指令，则在浮点单元内执行存储指令的存储数据部分。

公开(公告)号：US06289428B1

公开(公告)日：2001-09-11

申请号：US09366599

申请日：1999-08-03

申请人： John Edward Derrick ,  Hung Qui Le ,  David James Shippy ,  Larry Edward Thatcher

发明人： John Edward Derrick ,  Hung Qui Le ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F1202

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F12/04

摘要： A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment. The first and second data segments are merged together. All of the instructions executed by the processor are constrained by the memory boundary and do not access memory across the memory boundary.

摘要翻译： 公开了一种超标量处理器和方法，用于从未对准的数据地址有效地恢复。 处理器包括划分成多个可寻址存储器单元的存储器件。 多个可寻址存储器单元中的每一个具有第一多个字节的宽度。 确定存储器访问指令中包括的数据地址是否不对齐。 如果数据地址包括位于第一可寻址存储器单元中的第一数据段和位于第二可寻址存储器单元中的第二数据段，其中第一和第二数据段由可寻址存储器单元边界分隔，则该数据地址未对准。 响应于确定数据地址未对准，执行访问第一存储器单元并获得第一数据段的第一内部指令。 执行访问第二存储器单元并获得第二数据段的第二内部指令。 第一和第二数据段合并在一起。 由处理器执行的所有指令都受到存储器边界的约束，并且不会跨越存储器边界访问存储器。

公开(公告)号：US06237081B1

公开(公告)日：2001-05-22

申请号：US09213319

申请日：1998-12-16

申请人： Hung Qui Le ,  Larry Edward Thatcher ,  Bruce Joseph Ronchetti ,  David James Shippy

发明人： Hung Qui Le ,  Larry Edward Thatcher ,  Bruce Joseph Ronchetti ,  David James Shippy

IPC分类号： G06F932

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

摘要： A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.

摘要翻译： 处理器（100）包括具有用于向执行单元（140）发出指令的发布队列（144）的发布单元（125）。 执行单元（140）可接受并执行该指令或产生拒绝信号。 在发出每条指令之后，发出队列（144）保留发出的关键周期指令。 在关键时段之后，发布队列（144）可以放弃发出的指令，除非执行单元（140）已经产生了拒绝信号。 如果执行单元（140）已经产生了拒绝信号，则指令最终在发布队列（144）中被标记为可重新发行。 可以根据执行单元（140）的拒绝的性质来修改拒绝指令从重新发行保持的时间长度。 此外，执行单元（140）可以响应于某些拒绝条件进行校正动作，使得可以在重新发布时完全执行该指令。

公开(公告)号：US06654869B1

公开(公告)日：2003-11-25

申请号：US09428399

申请日：1999-10-28

申请人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore

IPC分类号： G06F500

CPC分类号： G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

摘要翻译： 微处理器包括提取单元，指令分解单元以及调度和完成控制逻辑。 提取单元从指令高速缓存中检索一组指令。 指令解码单元接收所提取的指令集，并将该组指令组织到指令组中。 调度和完成逻辑将组标签分配给指令组，并将组标记记录在完成表的条目中，以跟踪包括指令组的指令的完成状态。 调度和控制逻辑可以在对应于每个指令组的完成表条目中记录单个指令地址。 优选地，单指令地址是指令组中的第一指令的指令地址。 响应于检测到指令组中的指令产生的异常，处理器可以刷新指令组。

公开(公告)号：US06631463B1

公开(公告)日：2003-10-07

申请号：US09436103

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  John Anthony Moore ,  Kevin Franklin Reick ,  Edward John Silha

发明人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  John Anthony Moore ,  Kevin Franklin Reick ,  Edward John Silha

IPC分类号： G06F900

CPC分类号： G06F9/382 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3861

摘要： A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.

摘要翻译： 提出了一种用于在数据处理系统中的流水线处理器内修补有问题的指令的方法和装置。 获取多个指令，并且将多个指令与至少一个匹配条件进行匹配以生成匹配的指令。 匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。 可以使用伴随指令的匹配位通过指令流水线来标记匹配指令。 匹配的指令被替换为内部操作码或内部指令，使指令调度单元进行特殊的软件中断。 然后通过执行导致有问题的指令的期望的逻辑操作的一组指令来修补有问题的指令。

公开(公告)号：US06473850B1

公开(公告)日：2002-10-29

申请号：US09389197

申请日：1999-09-02

申请人： Hoichi Cheong ,  R. William Hay ,  James Allan Kahle ,  Hung Qui Le

发明人： Hoichi Cheong ,  R. William Hay ,  James Allan Kahle ,  Hung Qui Le

IPC分类号： G06F938

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3834

摘要： An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.

摘要翻译： ISYNC指令不会导致无条件地抛出推测分派或获取的指令（在ISYNC指令之后调度或取出的指令）。 本发明检测改变机器状态并需要上下文同步完成的任何指令的发生; 这些指令称为上下文同步所需指令。 当上下文同步所需指令完成时，本发明设置一个标志以注意该条件的发生。 当ISYNC指令完成时，如果上下文同步所需的标志是活动的，本发明引起冲洗并在ISYNC之后重新指定该指令。 然后，本发明重置上下文同步所需标志。 如果上下文同步所需的标志不是活动的，则本发明不产生刷新操作。

公开(公告)号：US06430678B1

公开(公告)日：2002-08-06

申请号：US09363463

申请日：1999-07-29

申请人： James Allan Kahle ,  Hung Qui Le ,  Lee Evan Eisen ,  John Edward Derrick ,  Robert William Hay

发明人： James Allan Kahle ,  Hung Qui Le ,  Lee Evan Eisen ,  John Edward Derrick ,  Robert William Hay

IPC分类号： G06F930

CPC分类号： G06F9/30018 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.

摘要翻译： 通过使用指令排序器单元记分板提供XER记分板功能。 如果XER由前一条指令使用，记分板位将被置位。 如果获取使用XER的新指令，则生成对XER的虚拟读取以测试记分板位以确定记分板位是否设置。 如果执行虚拟读取时记分板位未设置，则X形式的字符串将继续执行。 如果在执行虚拟机时设置了记分板位，则流水线停止，直到记分板位被清除，然后执行填充有生成的填充IOP（虚拟或NOP）的X形式字符串。 执行访问指令后，记分板位被清除。