Roll-On Liquid Applicator
    1.
    发明申请

    公开(公告)号:US20180000223A1

    公开(公告)日:2018-01-04

    申请号:US15542900

    申请日:2016-06-10

    CPC classification number: A45D34/041 A45D2200/054

    Abstract: A roll-on liquid applicator having an applicator ball disposed within a dispensing chamber and a spring element with a valve head portion. The spring element effects a distally-directed force to press the valve head against the valve opening to maintain a sealing closure of the valve opening against flow of the liquid from the feed chamber into the dispensing chamber. The valve head has a ball support structure which extends distally through the valve opening to contact with the applicator ball so that when the ball is inwardly displaced by force applied thereto, the valve head moves axially inward from the closed-valve position to the open-valve position, thereby moving the valve head from the closed-valve position in contact with the valve opening toward the open-valve position which allows liquid from the feed chamber to enter the dispensing chamber.

    Suck-Back Liquid Dispensing Valve and Valve Assembly

    公开(公告)号:US20170080441A1

    公开(公告)日:2017-03-23

    申请号:US14858928

    申请日:2015-09-18

    Abstract: A suck-back valve selectively actuatable for dispensing liquid in its open condition from an associated liquid storage container, and for avoiding continued presence of excess dispensed liquid about the exit orifice in the closed condition of the valve, is formed at least in part of a spring member and a pin. The spring member includes a distal web that defines a valve seat and a dispensed liquid exit orifice, a proximal web, and a plurality of flexibly elastic bands helically connecting the distal and proximal webs. The pin includes an elongated shaft having a proximal end secured to the proximal web and carrying a substantially hollow frustoconical cone at its distal end. The cone has an outer valving surface for releasable abutment with the valve seat and the shaft has a bore of predetermined cross-sectional extent defined longitudinally along and within the shaft to create a continuous fluid passageway through and along the pin. Dispensed liquid remaining proximate the exit orifice is sucked back into the liquid container through the shaft bore as the valve returns from its open to its closed condition under the return urgency of the elastic bands.

    METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
    3.
    发明申请
    METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER 有权
    用于形成具有顶部氧化物间隔物的存储单元的方法

    公开(公告)号:US20110233647A1

    公开(公告)日:2011-09-29

    申请号:US12891310

    申请日:2010-09-27

    CPC classification number: H01L27/11568 H01L21/28282 H01L29/792

    Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

    Abstract translation: 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域,其中多个源极/漏极区域形成在沟槽之间,在多个源极/漏极区域上方和沟槽中形成第一氧化物层,形成电荷存储层 在电荷存储层的分离部分之间,在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层,并且在第二氧化物层上方形成多晶硅层。

    METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
    4.
    发明申请
    METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER 有权
    用于形成具有顶部氧化物间隔物的存储单元的方法

    公开(公告)号:US20120181601A1

    公开(公告)日:2012-07-19

    申请号:US13428848

    申请日:2012-03-23

    CPC classification number: H01L27/11568 H01L21/28282 H01L29/792

    Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

    Abstract translation: 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域,其中多个源极/漏极区域形成在沟槽之间,在多个源极/漏极区域上方和沟槽中形成第一氧化物层,形成电荷存储层 在电荷存储层的分离部分之间,在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层,并且在第二氧化物层上方形成多晶硅层。

    METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中形成窄结构的方法

    公开(公告)号:US20110156130A1

    公开(公告)日:2011-06-30

    申请号:US13044313

    申请日:2011-03-09

    Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

    Abstract translation: 在半导体器件中形成多个导电结构的方法包括在掩模的侧表面附近形成间隔物,其中掩模和间隔物形成在导电层上。 该方法还包括蚀刻未被间隔物或掩模覆盖的导电层的一部分中的至少一个沟槽。 该方法还可以包括在半导体器件上沉积材料,去除掩模并蚀刻导电层以去除未被间隔物或材料覆盖的导电层的部分,其中导电层的其余部分形成导电结构。

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