公开(公告)号：US08202779B2

公开(公告)日：2012-06-19

申请号：US12891310

申请日：2010-09-27

Applicant: Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

Inventor： Shenqing Fang ,  Angela Hui ,  Gang Xue ,  Alexander Nickel ,  Kashmir Sahota ,  Scott Bell ,  Chun Chen ,  Wai Lo

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/792

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract translation: 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US20110233647A1

公开(公告)日：2011-09-29

申请号：US12891310

申请日：2010-09-27

Applicant: Shenqing FANG ,  Angela HUI ,  Gang XUE ,  Alexander NICKEL ,  Kashmir SAHOTA ,  Scott BELL ,  Chun CHEN ,  Wai LO

Inventor： Shenqing FANG ,  Angela HUI ,  Gang XUE ,  Alexander NICKEL ,  Kashmir SAHOTA ,  Scott BELL ,  Chun CHEN ,  Wai LO

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/792

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract translation: 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

公开(公告)号：US07465644B1

公开(公告)日：2008-12-16

申请号：US11258209

申请日：2005-10-26

Applicant: Simon S. Chan ,  Weidong Qian ,  Scott Bell ,  Phillip Jones ,  Allison Holbrook

Inventor： Simon S. Chan ,  Weidong Qian ,  Scott Bell ,  Phillip Jones ,  Allison Holbrook

IPC: H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/76202

Abstract: A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical isolation region formed in the exposed portion of the semiconducting layer, where the isolation region does not substantially encroach a region beneath the layer of aluminum oxide.

Abstract translation: 用于电绝缘半导体器件的结构包括半导体层和在半导体层上以图案形成的氧化铝层，其中图案暴露半导体层的一部分。 该结构还包括形成在半导体层的暴露部分中的电隔离区域，其中隔离区域基本上不侵蚀氧化铝层下面的区域。

公开(公告)号：US20070222606A1

公开(公告)日：2007-09-27

申请号：US11388043

申请日：2006-03-23

Applicant: William Phipps ,  Alberto Rodriguez ,  Scott Bell ,  Heiko Rommelmann

Inventor： William Phipps ,  Alberto Rodriguez ,  Scott Bell ,  Heiko Rommelmann

IPC: G08B13/14

CPC classification number: G06K17/0022 ,  G06K7/0008 ,  G06K7/10178 ,  G06K19/0723

Abstract: An RFID bridge antenna is positioned between a tag antenna associated with a tag and a reader antenna associated with a reader. The bridge includes at least two RF antenna elements spaced apart from one another and coupled together by an electrical conductor. The first RF antenna element is located proximate to the tag antenna and the second RF antenna element is located proximate to the reader antenna. An electromagnetic carrier signal transmitted by the reader antenna is received by one of the RF antenna element and retransmitted to the tag antenna by the other RF antenna element, increasing the distance over which the tag can communicate with the reader. Where the tag is attached to a packaged object, the RFID bridge antenna may be included in the package to allow wireless data communication between the tag and a reader. The reader may also be located external to the package. For example, one of the RF antenna elements may be attached to a label on the package, allowing data stored in the tag to be extracted by the external reader. The object may be a module, also known as a customer replaceable unit (CRU), and the tag may be configured as a customer replaceable unit monitor (CRUM). The module may take the form of a container having a closure cap equipped with a tag and the container may be stored in a cabinet along with an RFID bridge antenna mounted on the cabinet door to establish data communication between the tag and a reader.

Abstract translation: RFID桥接天线位于与标签相关联的标签天线和与读取器相关联的读取器天线之间。 该桥包括彼此间隔开并通过电导体耦合在一起的至少两个RF天线元件。 第一RF天线元件位于标签天线附近，第二RF天线元件位于读取器天线附近。 由读取器天线发送的电磁载波信号由RF天线元件中的一个接收，并由另一个RF天线元件重传到标签天线，从而增加标签可与读取器通信的距离。 在标签连接到打包对象的地方，RFID桥接天线可以包括在包装中，以允许标签和读取器之间的无线数据通信。 阅读器也可以位于包装的外部。 例如，RF天线元件中的一个可以附接到包装上的标签，从而允许由外部读取器提取存储在标签中的数据。 对象可以是模块，也称为客户可更换单元（CRU），并且标签可以被配置为客户可更换单元监视器（CRUM）。 模块可以采用具有装有标签的封闭盖的容器的形式，并且容器可以与安装在柜门上的RFID桥接天线一起存储在柜中，以建立标签和读取器之间的数据通信。

公开(公告)号：US20060223305A1

公开(公告)日：2006-10-05

申请号：US11098049

申请日：2005-04-04

Applicant: Phillip Jones ,  Mark Chang ,  Scott Bell

Inventor： Phillip Jones ,  Mark Chang ,  Scott Bell

IPC: H01L21/4763

CPC classification number: H01L21/32139 ,  H01L21/3088 ,  H01L21/31144

Abstract: A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

Abstract translation: 降低抗反射涂层结构中的特征的关键尺寸的方法可以利用聚合剂。 抗反射涂层结构可用于形成各种集成电路结构。 抗反射涂层可用于形成由多晶硅和电介质层，导电线或其它IC结构组成的栅叠层。 聚合剂可以包括碳，氢和氟。

公开(公告)号：US06642152B1

公开(公告)日：2003-11-04

申请号：US09812206

申请日：2001-03-19

Applicant: Che-Hoo Ng ,  Scott Bell ,  Anne Sanderfer ,  Christopher Lee Pike

Inventor： Che-Hoo Ng ,  Scott Bell ,  Anne Sanderfer ,  Christopher Lee Pike

IPC: H01L21302

CPC classification number: H01L21/0338 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144

Abstract: The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about 2500 Å formed over a semiconductor structure. In one aspect of the present invention, the method includes providing a semiconductor substrate having a device film layer formed thereon. An ultra thin resist is then deposited over the device film layer. The ultra thin resist is patterned according to a desired structure or feature using conventional photolithography techniques. Following development, the ultra thin resist is implanted with a dopant. After the implantation is substantially completed, the device film layer is anisotropically etched.

Abstract translation: 本发明涉及一种降低超薄抗蚀剂特征的线宽的系统和方法。 本发明通过对在半导体结构上形成的厚度小于约2500埃的超薄抗蚀剂施加致密化工艺来实现这一目的。 在本发明的一个方面，该方法包括提供其上形成有器件膜层的半导体衬底。 然后将超薄抗蚀剂沉积在器件膜层上。 根据期望的结构或特征，使用常规光刻技术将超薄抗蚀剂图案化。 在显影之后，用超声波光刻胶注入掺杂剂。 在基本完成注入之后，将各向异性蚀刻器件膜层。

公开(公告)号：US6121155A

公开(公告)日：2000-09-19

申请号：US205590

申请日：1998-12-04

Applicant: Chih-Yuh Yang ,  Scott Bell ,  Qi Xiang

Inventor： Chih-Yuh Yang ,  Scott Bell ,  Qi Xiang

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/302

CPC classification number: H01L21/82385 ,  H01L21/3088 ,  H01L21/31116

Abstract: The present invention provides a process for self-limiting trim etch of patterned photoresist that will allow integrated circuit fabrication to achieve smaller integrated circuit component features and greatly reduce final critical dimension drift or variation. Trim time is set in a plateau region of the critical dimension loss process curve.

Abstract translation: 本发明提供了一种用于图案化光致抗蚀剂的自限制微调蚀刻的方法，其将允许集成电路制造实现更小的集成电路组件特征并大大减少最终临界尺寸漂移或变化。 修剪时间设置在临界尺寸损失过程曲线的平台区域。

公开(公告)号：US20250137761A1

公开(公告)日：2025-05-01

申请号：US18384504

申请日：2023-10-27

Applicant: Scott Bell

Inventor： Scott Bell

IPC: F41A21/30

Abstract: A firearm sound suppression system may include, but is not limited to: a tubular body portion defining an entry aperture and an exit aperture; one or more baffles disposed inside the tubular body portion at locations along the length of the tubular body portion, the one or more baffles including: a central aperture, wherein the entry aperture, the one or more baffles, and the exit aperture are co-aligned to form a bore through the firearm sound suppression device.

公开(公告)号：US20180000223A1

公开(公告)日：2018-01-04

申请号：US15542900

申请日：2016-06-10

Applicant: James BELL ,  Scott BELL

Inventor： James BELL ,  Scott BELL

IPC: A45D34/04

CPC classification number: A45D34/041 ,  A45D2200/054

Abstract: A roll-on liquid applicator having an applicator ball disposed within a dispensing chamber and a spring element with a valve head portion. The spring element effects a distally-directed force to press the valve head against the valve opening to maintain a sealing closure of the valve opening against flow of the liquid from the feed chamber into the dispensing chamber. The valve head has a ball support structure which extends distally through the valve opening to contact with the applicator ball so that when the ball is inwardly displaced by force applied thereto, the valve head moves axially inward from the closed-valve position to the open-valve position, thereby moving the valve head from the closed-valve position in contact with the valve opening toward the open-valve position which allows liquid from the feed chamber to enter the dispensing chamber.

公开(公告)号：US20120181601A1

公开(公告)日：2012-07-19

申请号：US13428848

申请日：2012-03-23

Applicant: Shenqing FANG ,  Angela HUI ,  Gang XUE ,  Alexander NICKEL ,  Kashmir SAHOTA ,  Scott BELL ,  Chun CHEN ,  Wai LO

Inventor： Shenqing FANG ,  Angela HUI ,  Gang XUE ,  Alexander NICKEL ,  Kashmir SAHOTA ,  Scott BELL ,  Chun CHEN ,  Wai LO

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/792

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract translation: 公开了制造具有间隔层的半导体存储单元的方法。 一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层 在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。 该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。 在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。