公开(公告)号：US06516388B1

公开(公告)日：2003-02-04

申请号：US09662295

申请日：2000-09-15

申请人： James E. McCormick, Jr. ,  Stephen R. Undy

发明人： James E. McCormick, Jr. ,  Stephen R. Undy

IPC分类号： G06F1202

CPC分类号： G06F12/123 ,  G06F12/0862

摘要： In a cache which writes new data over less recently used data, methods and apparatus which dispense with the convention of marking new cache data as most recently used. Instead, non-referenced data is marked as less recently used when it is written into a cache, and referenced data is marked as more recently used when it is written into a cache. Referenced data may correspond to fetch data, and non-referenced data may correspond to prefetch data. Upon fetch of a data value from the cache, its use status may be updated to more recently used. The methods and apparatus have the affect of preserving (n−1)/n of a cache's entries for the storage of fetch data, while limiting the storage of prefetch data to 1/n of a cache's entries. Pollution which results from unneeded prefetch data is therefore limited to 1/n of the cache. In reality, however, pollution from unneeded prefetch data will be significantly less, as many prefetch data values will ultimately be fetched prior to their overwrite with new data, and upon their fetch, their use status can be upgraded to most recently used, thus ensuring their continued maintenance in the cache.

摘要翻译： 在通过较少使用的数据写入新数据的缓存中，不考虑最近使用的标记新的高速缓存数据的约定的方法和装置。 相反，未引用的数据在写入高速缓存时被标记为最近不被使用，并且被引用的数据被标记为在写入高速缓存时最近被使用的数据。 被引用的数据可以对应于获取数据，并且非参考数据可对应于预取数据。 从缓存中获取数据值时，其使用状态可能会更新到最近使用的状态。 这些方法和装置具有保存（n-1）/ n的缓存条目以存储获取数据的效果，同时将预取数据的存储限制到缓存的条目的1 / n。 因此，不必要的预取数据导致的污染限制在缓存的1 / n。 然而，实际上，不必要的预取数据的污染将会明显减少，因为在使用新数据覆盖之前，最终将获取许多预取数据值，并且在获取时，可以将其使用状态升级到最近使用，从而确保 他们在缓存中继续维护。

公开(公告)号：US06629167B1

公开(公告)日：2003-09-30

申请号：US09506777

申请日：2000-02-18

申请人： Stephen Undy ,  James E. McCormick, Jr.

发明人： Stephen Undy ,  James E. McCormick, Jr.

IPC分类号： G06F300

CPC分类号： G06F9/3824 ,  G06F9/3867

摘要： An apparatus for and a method of decoupling at least two multi-stage pipelines are described. At least two paths of data through which data from the first pipeline is send to the second pipeline are provided. During a pipelined execution of a task in the at least two pipelines, the second pipeline may not require every data produced in the first pipeline to process at least some subset of the task. The first pipeline may not be able to produce all data required by each of the stages of the second pipeline. One of the two data paths provides an early data path for a type of data that becomes available in a stage of the first pipeline and that may be processed in a stage of the second pipeline early in time. The other of the two data paths provides a late data path for a type of data that becomes available in a stage of the first pipeline and that may be processed in a stage of the second pipeline later in time. Each data path may comprise a buffer, e.g., a FIFO.

摘要翻译： 描述了用于解耦至少两个多级管线的装置和方法。 提供了将来自第一管线的数据发送到第二管道的至少两条数据路径。 在所述至少两条管线中的任务的流水线执行期间，所述第二流水线可以不要求在所述第一流水线中产生的每个数据来处理所述任务的至少一些子集。 第一管道可能无法产生第二管道的每个阶段所需的所有数据。 两个数据路径中的一个为第一管道的阶段中可用的数据类型提供早期数据路径，并且可以在时间早期在第二管道的阶段中进行处理。 两个数据路径中的另一个为第一流水线的阶段中可用的数据类型提供了一个延迟的数据路径，并且可以在稍后的第二管道的阶段中处理数据路径。 每个数据路径可以包括缓冲器，例如FIFO。

公开(公告)号：US09092346B2

公开(公告)日：2015-07-28

申请号：US13992354

申请日：2011-12-22

申请人： James E. McCormick, Jr.

发明人： James E. McCormick, Jr.

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30043 ,  G06F9/3842 ,  G06F12/0802 ,  G06F12/0855 ,  G06F2212/507 ,  Y02D10/13

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative cache modification design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a cache communicably interfaced with the data bus; a pipeline communicably interfaced with the data bus, in which the pipeline is to receive a store instruction corresponding to a cache line to be written to cache; caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline; and cache line validation logic to determine if the cache line written into the cache is valid or invalid, in which the cache line validation logic is to invalidate the cache line speculatively written into the cache when determined invalid and further in which the store instruction is allowed to retire from the pipeline when the cache line is determined to be valid.

摘要翻译： 根据本文公开的实施例，提供了用于实现推测性缓存修改设计的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地连接的缓存; 与数据总线可通信地连接的流水线，其中流水线将接收与要写入高速缓存的高速缓存行相对应的存储指令; 高速缓存逻辑，以便在存储指令从流水线退出之前执行高速缓存行的推测高速缓存写入高速缓存; 和高速缓存行验证逻辑，以确定写入高速缓存的高速缓存行是否有效或无效，其中高速缓存行验证逻辑将在确定为无效时将推测性写入高速缓存的高速缓存行无效，并且进一步允许存储指令 当缓存行被确定为有效时从管道中退出。

公开(公告)号：US07747844B2

公开(公告)日：2010-06-29

申请号：US11095072

申请日：2005-03-31

申请人： James E. McCormick, Jr. ,  James R. Callister ,  Susith R. Fernando

发明人： James E. McCormick, Jr. ,  James R. Callister ,  Susith R. Fernando

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F11/3476 ,  G06F2201/86

摘要： Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor. The exemplary system embodiment may also include logic for traversing the instruction and state data on a cycle count basis. The exemplary system may also include logic for traversing the instruction and state data on a retirement count basis.

摘要翻译： 描述与获取与性能监视事件相关联的指令地址相关联的系统，方法，介质和其他实施例。 一个示例性系统实施例包括用于记录与由流水线处理器相关联的性能监视逻辑可计数的事件相关联的指令和状态数据的逻辑。 示例性系统实施例还可以包括用于以周期计数为基础遍历指令和状态数据的逻辑。 示例性系统还可以包括用于在退休计数的基础上遍历指令和状态数据的逻辑。