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公开(公告)号：US5293349A
公开(公告)日：1994-03-08
申请号：US720099
申请日：1991-06-24
CPC分类号： G11C8/16 , Y10S257/903 , Y10S257/904
摘要： A memory cell constructed in accordance with the present invention includes a node operable to present an electrical level representing a first state or a second state. Further included is a first switching device having a first terminal connected to the node such that if the first switching device were to close, the electrical level at the node would be connected to a second terminal of the first switching device. Additionally, second and third switching devices are provided both having first and second terminals and both operable to switch as a function of the state at the node. Finally, a single control switching device is provided in association with the second and third switching devices wherein a control signal switches the control switching device such that the state at the node may be determined by connecting to the first terminals of the second and third switching devices.
摘要翻译： 根据本发明构造的存储单元包括可操作以呈现表示第一状态或第二状态的电平面的节点。 还包括第一开关装置，其具有连接到节点的第一端子，使得如果第一开关装置关闭，则节点处的电平将连接到第一开关装置的第二端子。 另外，第二和第三开关装置被提供为具有第一和第二端子，并且两者都可操作以根据节点处的状态来切换。 最后，与第二和第三开关装置相关联地提供单个控制开关装置，其中控制信号切换控制切换装置，使得可以通过连接到第二和第三开关装置的第一端子来确定节点处的状态 。
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2.发明授权
公开(公告)号：US5148065A
公开(公告)日：1992-09-15
申请号：US723089
申请日：1991-06-28
申请人： William R. Krenik , Louis J. Izzi
发明人： William R. Krenik , Louis J. Izzi
IPC分类号： H03K17/041 , H03K17/16
CPC分类号： H03K17/162 , H03K17/04106
摘要： Capacitance compensation techniques are used to reduce capacitive effects that impact on the performance of current steering circuits (FIG. 1). In an isolation technique (FIGS. 2a-2e), a resistor (R) or a diode (D) is coupled to a data-switched transistor to dampen voltage perturbations associated with the gate-to-source capacitance. In a design variable technique FIGS. 3a-3d), a transistor (PDV) is included in either the output or ground legs of the current steering circuit to provide a design variable to counteract the capacitive effects of the associated data-switched (PDX/NDX) or voltage-controlled (PREF) transistor. In a bipolar substitution technique (FIG. 4), a data-switched bipolar transistor (QDX) is substituted for the data-switched MOS transistor, and made sufficiently small to significantly reduce junction capacitance. In addition, capacitive effects can be reduced by introducing fabrication alterations (FIGS. 5a-5b), such as fabrication layouts in which the source contact is made within a U-shaped gate (FIG. 5a), and in which moat perimeter is contoured (FIG. 5b) for minimal gate area consistent with standard gate/contact spacing requirements.
摘要翻译： 电容补偿技术用于减少影响当前转向电路性能的电容效应（图1）。 在隔离技术（图2a-2e）中，电阻器（R）或二极管（D）被耦合到数据交换晶体管以抑制与栅极 - 源极电容相关联的电压扰动。 在设计变量技术中， 在当前转向电路的输出或接地支路中包括晶体管（PDV），以提供设计变量来抵消相关数据交换（PDX / NDX）或电压控制（PDX / NDX）的电容效应， PREF）晶体管。 在双极替代技术（图4）中，数据开关双极晶体管（QDX）代替数据交换MOS晶体管，并且足够小以显着地减小结电容。 此外，通过引入制造改变（图5a-5b）可以减少电容效应，诸如在U形门（图5a）内形成源极接触的制造布局，并且其中护城河周边是轮廓的 （图5b），用于与标准门/接触间隔要求一致的最小栅极面积。
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公开(公告)号：US5596583A
公开(公告)日：1997-01-21
申请号：US734344
申请日：1991-07-19
申请人： William R. Krenik , Louis J. Izzi , Chenwei J. Yin
发明人： William R. Krenik , Louis J. Izzi , Chenwei J. Yin
摘要： Test circuitry (90) is provided which includes a multiplexer (118) for selectively receiving multiple bit control words defining test functions to be executed by said test circuitry and for outputting data from said test circuitry. A plurality of digital data inputs (96) are provided for receiving multiple bit words of digital data and a plurality of analog data inputs (98) are provided for receiving analog data. A register (120) is coupled to multiplexer (118) for storing a one of the multiple bit words received by multiplexer (118). Control circuitry (122) is coupled to register (120) for controlling execution of the test function defined by the control word being held in register (120). First test circuitry (112) is coupled to digital data inputs (96) and control circuitry (122) for passing digital data words received at digital data inputs (96) to multiplexer (118) for output in response to a first control word of said control words being held in register (120).
摘要翻译： 提供了测试电路（90），其包括多路复用器（118），用于选择性地接收定义由所述测试电路执行的测试功能的多个位控制字，并用于从所述测试电路输出数据。 提供多个数字数据输入（96）用于接收数字数据的多位字，并且提供多个模拟数据输入（98）用于接收模拟数据。 寄存器（120）耦合到多路复用器（118），用于存储由多路复用器（118）接收的多个位字之一。 控制电路（122）耦合到寄存器（120），用于控制由保持在寄存器（120）中的控制字定义的测试功能的执行。 第一测试电路（112）耦合到数字数据输入（96）和控制电路（122），用于将数字数据输入（96）接收的数字数据字传送到多路复用器（118），以响应于所述第一控制字 控制字被保存在寄存器（120）中。
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4.发明授权Color palette timing and control with circuitry for producing an additional clock cycle during a clock disabled time period 失效调色板定时和控制，具有在时钟禁止时间段内产生额外时钟周期的电路
公开(公告)号：US5379408A
公开(公告)日：1995-01-03
申请号：US789725
申请日：1991-11-08
申请人： Louis J. Izzi , William R. Krenik
发明人： Louis J. Izzi , William R. Krenik
CPC分类号： G09G5/18
摘要： A clock control circuit 84 is provided which includes circuitry 98 for selecting a master clock from among at least two input clocks provided to clock control circuit 94, the selection made in response to master clock selection control signals. Circuitry 104 is coupled to circuitry for selecting 98 for providing at least first and second divided down clocks each being of a different divide ratio of the master clock. Circuitry 108 is coupled to circuitry for providing divided down clocks 104 for selecting an output clock from between at least the first and second divided down clocks in response to output clock selection control signals received by clock control circuit 84. Circuitry 120 is provided coupled to circuitry for selecting an output clock 108 for selectively controlling the output of the output clock, circuitry for controlling output clock 120 enabling output of the output clock in response to a first output clock control signal received by clock control circuitry 84 and disabling output of the output clock in response to a second output clock output control signal received by clock control circuit 84. Circuitry 120 is further operable to selectively output an additional output clock cycle in response to a control signal during a period when circuitry for controlling 120 has disabled output of the output clock.
摘要翻译： 提供了时钟控制电路84，其包括用于从提供给时钟控制电路94的至少两个输入时钟中选择主时钟的电路98，响应于主时钟选择控制信号进行选择。 电路104耦合到用于选择98的电路，用于提供至少第一和第二分频下降时钟，每个分频下降时钟具有主时钟的不同分频比。 电路108耦合到电路，用于提供用于响应于由时钟控制电路84接收的输出时钟选择控制信号从至少第一和第二分频时钟之间选择输出时钟的分频下降时钟104.电路120被耦合到电路 用于选择用于选择性地控制输出时钟的输出的输出时钟108，用于控制输出时钟120的电路，其能够响应于由时钟控制电路84接收的第一输出时钟控制信号输出输出时钟，并禁用输出时钟的输出 响应于由时钟控制电路84接收的第二输出时钟输出控制信号。电路120进一步可操作以响应于控制信号选择性地输出附加的输出时钟周期，在用于控制的电路120的电路已禁用输出的输出 时钟。
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公开(公告)号：US5699087A
公开(公告)日：1997-12-16
申请号：US333899
申请日：1994-11-03
申请人： William R. Krenik , Louis J. Izzi
发明人： William R. Krenik , Louis J. Izzi
CPC分类号： G09G5/06
摘要： A method is provided for accessing data stored in memory (76). First data appearing at outputs (102) of memory (76) are read during a first reading cycle in a sequence of reading cycles, the first data retrieved from a first location in memory (76) corresponding to a first address. At the end of the first reading cycle, the first address is stepped to produce a second address corresponding to a second location in memory (76). During an idle period following the first reading cycle and prior to a second reading cycle occurring next in the sequence of reading cycles, second data is prefetched from the second location in memory (76) such that the second data appears at the bitlines (102) of memory (76) at the start of the second reading cycle.
摘要翻译： 提供一种访问存储在存储器（76）中的数据的方法。 在第一读取周期期间以读取周期的顺序读出出现在存储器（76）的输出端（102）的第一数据，从存储器（76）中对应于第一地址的第一位置检索的第一数据。 在第一读取周期结束时，第一地址被步进以产生对应于存储器（76）中的第二位置的第二地址。 在第一读取周期之后的空闲时段期间和接下来在读取周期序列中发生第二读取周期之前，从存储器（76）中的第二位置预取第二数据，使得第二数据出现在位线（102）处， 的存储器（76）在第二读取周期的开始。
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6.发明授权Graphics system including an output buffer circuit with controlled Miller effect capacitance 失效图形系统包括具有受控米勒效应电容的输出缓冲电路
公开(公告)号：US5465058A
公开(公告)日：1995-11-07
申请号：US339057
申请日：1994-11-14
申请人： William R. Krenik , Louis J. Izzi
发明人： William R. Krenik , Louis J. Izzi
IPC分类号： H03K17/16 , H03K19/0175 , H03K19/094
CPC分类号： H03K17/164
摘要： An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.
摘要翻译： 集成电路缓冲器包括具有输出的源极跟随器输出晶体管，并且还通过降压电路连接到电源轨，从而在源极跟随器输出晶体管中引入受控量的米勒效应电容。 缓冲器还具有公共源极输出晶体管和连接在共源极输出晶体管和源极跟随器输出晶体管之间的单向导通电路。 还公开了其他缓冲器，调色板装置，计算机图形系统和方法。
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7.发明授权Graphics system including an output buffer circuit with controlled Miller effect capacitance 失效图形系统包括具有受控米勒效应电容的输出缓冲电路
公开(公告)号：US5365126A
公开(公告)日：1994-11-15
申请号：US127213
申请日：1993-09-27
申请人： William R. Krenik , Louis J. Izzi
发明人： William R. Krenik , Louis J. Izzi
IPC分类号： H03K17/16 , H03K19/092 , H03K19/094
CPC分类号： H03K17/164
摘要： An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.
摘要翻译： 集成电路缓冲器包括具有输出的源极跟随器输出晶体管，并且还通过降压电路连接到电源轨，从而在源极跟随器输出晶体管中引入受控量的米勒效应电容。 缓冲器还具有公共源极输出晶体管和连接在共源极输出晶体管和源极跟随器输出晶体管之间的单向导通电路。 还公开了其他缓冲器，调色板装置，计算机图形系统和方法。
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公开(公告)号：US5469195A
公开(公告)日：1995-11-21
申请号：US288137
申请日：1994-08-09
申请人： Henry T. Yung , Louis J. Izzi , William R. Krenik
发明人： Henry T. Yung , Louis J. Izzi , William R. Krenik
CPC分类号： H01L27/0805
摘要： An integrated circuit capacitor has a semiconductor die and a plurality of field effect transistors fabricated on the die and having gates, sources and drains. The gates are connected to each other as one side of the capacitor. The sources and drains are connected together as another side of the capacitor. A color palette has a die with circuitry including a dot clock buffer with transistors connected to supply rails and the integrated circuit capacitor having a plurality of the parallel-connected field effect transistors connected across the supply rails. The dot clock buffer has an output distributed directly to the rest of the circuitry. Other capacitors, buffers, systems and methods are also disclosed.
摘要翻译： 集成电路电容器具有半导体管芯和在管芯上制造并具有栅极，源极和漏极的多个场效应晶体管。 栅极作为电容器的一侧彼此连接。 源极和漏极连接在一起作为电容器的另一侧。 调色板具有包括具有连接到电源轨的晶体管的点时钟缓冲器的电路的芯片，并且集成电路电容器具有连接在电源轨上的多个并联连接的场效应晶体管。 点时钟缓冲器具有直接分配到电路的其余部分的输出。 还公开了其它电容器，缓冲器，系统和方法。
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公开(公告)号：US5274284A
公开(公告)日：1993-12-28
申请号：US647614
申请日：1991-01-24
申请人： William R. Krenik , Louis J. Izzi
发明人： William R. Krenik , Louis J. Izzi
IPC分类号： H03K17/16 , H03K19/092 , H03K19/20
CPC分类号： H03K17/164
摘要： An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.
摘要翻译： 集成电路缓冲器包括具有输出的源极跟随器输出晶体管，并且还通过降压电路连接到电源轨，从而在源极跟随器输出晶体管中引入受控量的米勒效应电容。 缓冲器还具有公共源极输出晶体管和连接在共源极输出晶体管和源极跟随器输出晶体管之间的单向导通电路。 还公开了其他缓冲器，调色板装置，计算机图形系统和方法。
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公开(公告)号：US5414447A
公开(公告)日：1995-05-09
申请号：US143333
申请日：1993-10-26
申请人： Louis J. Izzi , Richard E. Downing
发明人： Louis J. Izzi , Richard E. Downing
摘要： A frame buffer is provided, including a plurality of input nodes and a plurality of multiplexing circuits. Each multiplexing circuit has a first input coupled to a respective input node. First control circuitry is provided for selectively coupling a second input of each multiplexer circuit to outputs of others of the multiplexing circuits. Second control circuitry is coupled to each multiplexing circuit for selecting between the first and second inputs.
摘要翻译： 提供了一种帧缓冲器，包括多个输入节点和多个复用电路。 每个复用电路具有耦合到相应输入节点的第一输入。 提供第一控制电路用于将每个多路复用器电路的第二输入选择性地耦合到多路复用电路中的其他输出。 第二控制电路耦合到每个复用电路，用于在第一和第二输入之间进行选择。
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