公开(公告)号：US20060178764A1

公开(公告)日：2006-08-10

申请号：US11054261

申请日：2005-02-09

申请人： Andreas Bieswanger ,  Lee Eisen ,  James Fields ,  Michael Floyd ,  Bradley McCredie ,  Naresh Nayar

发明人： Andreas Bieswanger ,  Lee Eisen ,  James Fields ,  Michael Floyd ,  Bradley McCredie ,  Naresh Nayar

IPC分类号： G05B11/01 ,  G05B19/42

CPC分类号： G06F1/206

摘要： A method, apparatus and computer instructions are provided to autonomically monitor and adjust system characteristics based on a customer optimization goal specified in a policy or profile. An autonomic management component is implemented in firmware comprising a set of control algorithms. Response to reading system characteristics from a plurality of sensors, the autononmic management component selects at least one control algorithm from the set and the control algorithm adjusts the parameters of the system characteristic to optimize performance according to the optimization goal specified by the customer.

摘要翻译： 提供了一种方法，装置和计算机指令，用于基于在策略或简档中指定的客户优化目标自主地监视和调整系统特征。 在包括一组控制算法的固件中实现自主管理组件。 响应于多个传感器的读取系统特性，自动管理部件从集合中选择至少一个控制算法，并且控制算法根据客户指定的优化目标调整系统特性的参数以优化性能。

公开(公告)号：US20060149944A1

公开(公告)日：2006-07-06

申请号：US11002522

申请日：2004-12-02

申请人： Lee Eisen ,  Francis O'Connell

发明人： Lee Eisen ,  Francis O'Connell

IPC分类号： G06F9/44

CPC分类号： G06F9/3842 ,  G06F9/30058 ,  G06F9/30181 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3867

摘要： A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is selected. An indication is stored within each instruction that is the particular type of conditional branch instruction. A processor then fetches a first instruction from code that is to be executed. A determination is made regarding whether the first instruction includes the indication. In response to determining that the instruction includes the indication: speculative execution of the first instruction is prohibited, an actual location to which the first instruction will branch is resolved, and execution of the code is branched to the actual location. In response to determining that the instruction does not include the indication, the first instruction is speculatively executed.

摘要翻译： 公开了用于选择性地禁止推测性条件分支执行的方法，装置和计算机程序产品。 选择特定类型的条件分支指令。 指示存储在作为条件分支指令的特定类型的每个指令内。 然后处理器从要执行的代码中获取第一条指令。 确定第一指令是否包括指示。 响应于确定指令包括指示：禁止第一指令的推测执行，第一指令将分支的实际位置被解析，并且代码的执行被分支到实际位置。 响应于确定指令不包括指示，推测性地执行第一指令。

公开(公告)号：US20110153991A1

公开(公告)日：2011-06-23

申请号：US12645716

申请日：2009-12-23

申请人： FADI BUSABA ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

发明人： FADI BUSABA ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

IPC分类号： G06F9/312 ,  G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3867

摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。

公开(公告)号：US20060161762A1

公开(公告)日：2006-07-20

申请号：US11039498

申请日：2005-01-20

申请人： Lee Eisen ,  David Levitan ,  Francis O'Connell ,  Wolfram Sauer

发明人： Lee Eisen ,  David Levitan ,  Francis O'Connell ,  Wolfram Sauer

IPC分类号： G06F9/44

CPC分类号： G06F9/5011 ,  G06F9/3844 ,  G06F9/3851 ,  G06F2209/507 ,  Y02D10/22

摘要： A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.

摘要翻译： 用于管理用于推测性执行的处理系统资源使用的方法和逻辑装置降低与程序指令的无效推测执行相关联的功率和性能负担。 投机执行效率的度量用于减少分配给线程的资源，同时投机效率低。 应用的资源控制可以是分配给线程的指令获取的数量或执行时间片的数量。 或者或组合地，分配给线程的预取指令存储器的大小可能受到限制。 控制条件可以是正确的或不正确的猜测的数量与阈值的比较，正确到不正确的猜测的数量的比较，或比较复杂的评估者，比如不正确比例与总猜测的比例。

公开(公告)号：US08464030B2

公开(公告)日：2013-06-11

申请号：US12757330

申请日：2010-04-09

申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3017 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30058

摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.

摘要翻译： 一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。 至少接收一条指令。 至少对指令进行分析。 识别与该至少一条指令相关联的指令类型。 分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。 然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。 然后执行一组操作单元。

公开(公告)号：US09104399B2

公开(公告)日：2015-08-11

申请号：US12645716

申请日：2009-12-23

申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC分类号： G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3867

摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。

公开(公告)号：US20060101238A1

公开(公告)日：2006-05-11

申请号：US11228781

申请日：2005-09-16

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard Eickemeyer ,  Lee Eisen ,  Philip Emma ,  John Griswell ,  Zhigang Hu ,  Hung Le ,  Douglas Logan ,  Balaram Sinharoy

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard Eickemeyer ,  Lee Eisen ,  Philip Emma ,  John Griswell ,  Zhigang Hu ,  Hung Le ,  Douglas Logan ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3867

摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.

摘要翻译： 多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。 监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。 对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。 此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。 因此，处理器避免浪费电力不必要的或放置保持器提取。