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    INSTRUCTION FILTERING
    1.
    发明申请
    INSTRUCTION FILTERING 有权
    指令过滤

    公开(公告)号：US20130339683A1

    公开(公告)日：2013-12-19

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

    Mitigating instruction prediction latency with independently filtered presence predictors
    2.
    发明授权
    Mitigating instruction prediction latency with independently filtered presence predictors 有权
    用独立过滤的存在预测器缓解指令预测延迟

    公开(公告)号：US09152424B2

    公开(公告)日：2015-10-06

    申请号：US13523784

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/38 ,  G06F9/3806 ,  G06F9/3848

    摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.

    摘要翻译： 本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。 预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。 预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。 每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。 预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。 停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。

    Instruction filtering
    3.
    发明授权
    Instruction filtering 有权
    指令过滤

    公开(公告)号：US09135012B2

    公开(公告)日：2015-09-15

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

    MITIGATING INSTRUCTION PREDICTION LATENCY WITH INDEPENDENTLY FILTERED PRESENCE PREDICTORS
    4.
    发明申请
    MITIGATING INSTRUCTION PREDICTION LATENCY WITH INDEPENDENTLY FILTERED PRESENCE PREDICTORS 有权
    与独立过滤的预测者进行预防指示预测失效

    公开(公告)号：US20130339692A1

    公开(公告)日：2013-12-19

    申请号：US13523784

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/38 ,  G06F9/3806 ,  G06F9/3848

    摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.

    摘要翻译： 本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。 预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。 预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。 每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。 预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。 停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。

    SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION
    6.
    发明申请
    SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION 有权
    选择性阻塞分支指导预测

    公开(公告)号：US20130339696A1

    公开(公告)日：2013-12-19

    申请号：US13524402

    申请日：2012-06-15

    申请人： James J. Bonanno ,  Ulrich Mayer ,  Anthony Saporito ,  Chung-Lung K. Shum ,  Timothy J. Slegel

    发明人： James J. Bonanno ,  Ulrich Mayer ,  Anthony Saporito ,  Chung-Lung K. Shum ,  Timothy J. Slegel

    IPC分类号： G06F9/38

    CPC分类号： G06F9/38 ,  G06F9/30076 ,  G06F9/3844 ,  G06F9/3848

    摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

    摘要翻译： 实施例涉及选择性地阻止分支指令预测。 一个方面包括用于执行选择性分支预测的计算机系统。 系统包括存储器和处理器，并且系统被配置为执行方法。 该方法包括：根据检测分支预测阻断指令，在分支预测阻塞指令之后检测指令流中的分支预测分块指令并阻止预分支数量的分支指令的分支预测。

    Cache set replacement order based on temporal set recording
    8.
    发明授权
    Cache set replacement order based on temporal set recording 有权
    基于时间设置记录的缓存集替换顺序

    公开(公告)号：US08806139B2

    公开(公告)日：2014-08-12

    申请号：US13354894

    申请日：2012-01-20

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

    IPC分类号： G06F12/12

    CPC分类号： G06F12/0875 ,  G06F12/126

    摘要： A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.

    摘要翻译： 提供了用于高速缓存的高速缓存管理的技术。 处理电路在先前执行请求数据元素存储在高速缓存中的指令期间确定未命中和命中位置字段。 针对与请求存储数据元素的指令相对应的数据元素存储未命中和命中位置字段。 处理电路基于错过次数和/或命中位置字段将数据元素放置成分层次序。 命中位置字段包括与缓存中的数据元素相关的分层位置。