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公开(公告)号：US09891922B2
公开(公告)日：2018-02-13
申请号：US13524402
申请日：2012-06-15
CPC分类号： G06F9/38 , G06F9/30076 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
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公开(公告)号：US20130339696A1
公开(公告)日：2013-12-19
申请号：US13524402
申请日：2012-06-15
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30076 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
摘要翻译： 实施例涉及选择性地阻止分支指令预测。 一个方面包括用于执行选择性分支预测的计算机系统。 系统包括存储器和处理器，并且系统被配置为执行方法。 该方法包括：根据检测分支预测阻断指令，在分支预测阻塞指令之后检测指令流中的分支预测分块指令并阻止预分支数量的分支指令的分支预测。
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公开(公告)号：US20130339683A1
公开(公告)日：2013-12-19
申请号：US13523170
申请日：2012-06-14
申请人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/30 , G06F9/30047 , G06F9/3005 , G06F9/3806 , G06F9/3836
摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。
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公开(公告)号：US09135012B2
公开(公告)日：2015-09-15
申请号：US13523170
申请日：2012-06-14
申请人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
CPC分类号： G06F9/3844 , G06F9/30 , G06F9/30047 , G06F9/3005 , G06F9/3806 , G06F9/3836
摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。
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5.发明授权Mitigating instruction prediction latency with independently filtered presence predictors 有权用独立过滤的存在预测器缓解指令预测延迟公开(公告)号：US09152424B2
公开(公告)日：2015-10-06
申请号：US13523784
申请日：2012-06-14
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/38 , G06F9/3806 , G06F9/3848
摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.
摘要翻译： 本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。 预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。 预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。 每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。 预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。 停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。
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6.发明申请MITIGATING INSTRUCTION PREDICTION LATENCY WITH INDEPENDENTLY FILTERED PRESENCE PREDICTORS 有权与独立过滤的预测者进行预防指示预测失效公开(公告)号：US20130339692A1
公开(公告)日：2013-12-19
申请号：US13523784
申请日：2012-06-14
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/38 , G06F9/3806 , G06F9/3848
摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.
摘要翻译： 本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。 预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。 预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。 每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。 预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。 停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。
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公开(公告)号：US20130339691A1
公开(公告)日：2013-12-19
申请号：US13517779
申请日：2012-06-14
申请人： James J. Bonanno , Marcel Mitran , Brian R. Prasky , Joran Siu , Timothy J. Slegel , Alexander Vasilevskiy
发明人： James J. Bonanno , Marcel Mitran , Brian R. Prasky , Joran Siu , Timothy J. Slegel , Alexander Vasilevskiy
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/3806 , G06F9/3844
摘要： Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.
摘要翻译： 实施例涉及分支预测预加载。 一方面包括用于分支预测预加载的系统。 该系统包括耦合到处理电路的指令高速缓存和分支目标缓冲器（BTB），所述处理电路被配置为执行方法。 该方法包括从指令高速缓冲存储器中取出指令流中的多个指令，以及对指令流中的分支预测预加载指令进行解码。 基于分支预测预加载指令来确定预测转移指令的地址。 基于分支预测预加载指令来确定预测目标地址。 在分支预测预加载指令中识别掩码字段，并且基于掩码字段来确定分支指令长度。 基于执行分支预测预加载指令，BTB预先加载预测分支指令的地址，分支指令长度，分支类型和预测目标地址。
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公开(公告)号：US09146739B2
公开(公告)日：2015-09-29
申请号：US13517779
申请日：2012-06-14
申请人： James J. Bonanno , Marcel Mitran , Brian R. Prasky , Joran Siu , Timothy J. Slegel , Alexander Vasilevskiy
发明人： James J. Bonanno , Marcel Mitran , Brian R. Prasky , Joran Siu , Timothy J. Slegel , Alexander Vasilevskiy
CPC分类号： G06F9/30058 , G06F9/3806 , G06F9/3844
摘要： Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.
摘要翻译： 实施例涉及分支预测预加载。 一方面包括用于分支预测预加载的系统。 该系统包括耦合到处理电路的指令高速缓存和分支目标缓冲器（BTB），所述处理电路被配置为执行方法。 该方法包括从指令高速缓冲存储器中取出指令流中的多个指令，以及对指令流中的分支预测预加载指令进行解码。 基于分支预测预加载指令来确定预测分支指令的地址。 基于分支预测预加载指令来确定预测目标地址。 在分支预测预加载指令中识别掩码字段，并且基于掩码字段来确定分支指令长度。 基于执行分支预测预加载指令，BTB预先加载预测分支指令的地址，分支指令长度，分支类型和预测目标地址。
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9.发明授权Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs 有权通过故意停止分支指令，直到接收到延迟的分支预测或发生超时来减轻前瞻分支预测等待时间公开(公告)号：US08874885B2
公开(公告)日：2014-10-28
申请号：US12029543
申请日：2008-02-12
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3836 , G06F9/3848
摘要： Embodiments relate to mitigation of lookahead branch predication latency. An aspect includes receiving an instruction address in an instruction cache for fetching instructions in a microprocessor pipeline. Another aspect includes receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline. Another aspect includes determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor. Another aspect includes, based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction. Another aspect includes, based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline.
摘要翻译： 实施例涉及减轻前瞻分支预测延迟。 一个方面包括在指令高速缓存中接收用于在微处理器流水线中取指令的指令地址。 另一方面包括在耦合到微处理器流水线的分支存在预测器中接收指令地址。 另一方面包括通过分支存在预测器确定在所取出的指令中存在分支指令，其中分支指令可由分支目标缓冲器预测，并且未写入分支目标缓冲器的指令地址的任何指示也是 没有写入分支存在预测器。 另一方面包括：基于从分支存在预测器接收到分支指令的指示，保持分支指令。 另一方面包括基于从分支目标缓冲器接收到与分支指令相对应的分支预测，将所述保持的分支指令释放到流水线。
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10.发明授权Method, system and computer program product for an implicit predicted return from a predicted subroutine 失效用于预测子程序的隐式预测回报的方法，系统和计算机程序产品公开(公告)号：US07882338B2
公开(公告)日：2011-02-01
申请号：US12034066
申请日：2008-02-20
申请人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito, III , Robert J. Sonnelitter, III , Charles F. Webb
发明人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito, III , Robert J. Sonnelitter, III , Charles F. Webb
IPC分类号： G06F9/32
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/3806 , G06F9/3844
摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.
摘要翻译： 提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。 该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。 该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。 该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。 该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。
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