公开(公告)号：US20110311009A1

公开(公告)日：2011-12-22

申请号：US12819660

申请日：2010-06-21

申请人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： H04L7/00

CPC分类号： H04L1/205 ,  G01R13/0218

摘要： An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.

摘要翻译： 描述了一个模内范围。 在线范围可以包括一个或多个范围限幅器，相位扫描电路，电压扫描电路和眼图数据收集电路。 时钟和数据恢复电路可以接收输入信号，并输出恢复的时钟信号和恢复的比特流。 相位扫描电路可以接收恢复的时钟信号，并通过向恢复的时钟信号添加相位偏移来输出示波器时钟信号。 示波器限幅器可以接收电压阈值，示波器时钟信号和输入信号，并输出示波器位流。 眼图数据收集电路可以检测恢复的比特流中的一个或多个比特模式，并且单独或部分地基于范围比特流和恢复的比特流来修改一个或多个范围计数器的值。

公开(公告)号：US08208591B2

公开(公告)日：2012-06-26

申请号：US12819629

申请日：2010-06-21

申请人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： H04B1/10

CPC分类号： H04L25/03019 ,  H04L2025/03617 ,  H04L2025/03656 ,  H04L2025/037

摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.

摘要翻译： 描述了用于适配和/或优化接收机的均衡器的系统和技术。 可以通过修改一个或多个均衡参数来调整均衡器的行为。 在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。 然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。 具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。 接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值 。

公开(公告)号：US20110310947A1

公开(公告)日：2011-12-22

申请号：US12819629

申请日：2010-06-21

申请人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： H03H7/30

CPC分类号： H04L25/03019 ,  H04L2025/03617 ,  H04L2025/03656 ,  H04L2025/037

摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.

摘要翻译： 描述了用于适配和/或优化接收机的均衡器的系统和技术。 可以通过修改一个或多个均衡参数来调整均衡器的行为。 在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。 然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。 具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。 接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值 。

公开(公告)号：US08184757B2

公开(公告)日：2012-05-22

申请号：US12819660

申请日：2010-06-21

申请人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  Robert B. Lefferts ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： H04L7/00

CPC分类号： H04L1/205 ,  G01R13/0218

摘要： An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.

摘要翻译： 描述了一个模内范围。 在线范围可以包括一个或多个范围限幅器，相位扫描电路，电压扫描电路和眼图数据收集电路。 时钟和数据恢复电路可以接收输入信号，并输出恢复的时钟信号和恢复的比特流。 相位扫描电路可以接收恢复的时钟信号，并通过向恢复的时钟信号添加相位偏移来输出示波器时钟信号。 示波器限幅器可以接收电压阈值，示波器时钟信号和输入信号，并输出示波器位流。 眼图数据收集电路可以检测恢复的比特流中的一个或多个比特模式，并且单独或部分地基于范围比特流和恢复的比特流来修改一个或多个范围计数器的值。

公开(公告)号：US20110309857A1

公开(公告)日：2011-12-22

申请号：US12819650

申请日：2010-06-21

申请人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H03F1/56 ,  H03F2200/387 ,  H04L25/028

摘要： Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.

摘要翻译： 本发明的一些实施例提供一种电压模式发射机。 发射机可以包括配置电路，偏置电路和一组驱动器片。 每个驱动器片可以包括驱动输出值的驱动器晶体管。 每个驱动器片的输出可以与发射器的输出直接或电容耦合。 每个驱动器片还可以包括串联耦合到至少一些驱动晶体管的一个或多个阻抗匹配晶体管。 配置电路可以配置驱动器片段的子集，使得发射机的向下（或向上）阻抗在期望阻抗值的第一公差内。 偏置电路可以偏置驱动器片段子集中的每个驱动器片中的一个或多个阻抗匹配晶体管，使得上（或下））阻抗在下（或向上）阻抗的第二容限内。

公开(公告)号：US08477898B2

公开(公告)日：2013-07-02

申请号：US12819683

申请日：2010-06-21

申请人： James P. Flynn ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin ,  Dino A. Toffolon ,  Jasjeet Singh

发明人： James P. Flynn ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin ,  Dino A. Toffolon ,  Jasjeet Singh

IPC分类号： H03D3/24

CPC分类号： H03L7/183 ,  H03L7/081

摘要： One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

摘要翻译： 本发明的一个实施例提供了一种用于合成分数频率的锁相环（PLL）。 PLL可以包括1 / N分频器，压控振荡器（VCO），可编程相位混频器和相位检测器。 可编程相位混频器可以耦合在VCO的输出端和分频器的输入端之间，其中可编程相位混频器配置成从VCO接收输出时钟信号，并通过改变相位产生频率为f1的第一时钟信号 的输出时钟信号。 分频器被配置为从可编程相位混合器接收第一时钟信号，并产生频率为f2 = f1 / N的第二时钟信号。 相位检测器可以接收参考时钟信号和第二个时钟信号作为输入，并且相位检测器的输出可用于产生VCO的控制电压。

公开(公告)号：US20110310942A1

公开(公告)日：2011-12-22

申请号：US12819683

申请日：2010-06-21

申请人： James P. Flynn ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin ,  Dino A. Toffolon ,  Jasjeet Singh

发明人： James P. Flynn ,  Richard H. Steeves ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin ,  Dino A. Toffolon ,  Jasjeet Singh

IPC分类号： H03L7/00 ,  H04L7/00 ,  H04B1/38

CPC分类号： H03L7/183 ,  H03L7/081

摘要： One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

摘要翻译： 本发明的一个实施例提供了一种用于合成分数频率的锁相环（PLL）。 PLL可以包括1 / N分频器，压控振荡器（VCO），可编程相位混频器和相位检测器。 可编程相位混频器可以耦合在VCO的输出端和分频器的输入端之间，其中可编程相位混频器配置成从VCO接收输出时钟信号，并通过改变相位产生频率为f1的第一时钟信号 的输出时钟信号。 分频器被配置为从可编程相位混合器接收第一时钟信号，并产生频率为f2 = f1 / N的第二时钟信号。 相位检测器可以接收参考时钟信号和第二个时钟信号作为输入，并且相位检测器的输出可用于产生VCO的控制电压。

公开(公告)号：US08526551B2

公开(公告)日：2013-09-03

申请号：US12791755

申请日：2010-06-01

申请人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： H03D1/04

CPC分类号： G01R13/0272 ,  G01R31/2884 ,  G01R31/3171 ,  H04L25/03878 ,  H04L27/01

摘要： An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.

摘要翻译： 描述了包括接收数据路径的集成电路。 接收数据路径：对接收到的模拟信号进行均衡，基于时钟信号将所得到的均衡模拟信号转换为数字数据值，并恢复数字数据值中的时钟信号。 该集成电路还包括片上示波器。 示波器包括：两个比较器，一个相位旋转器，输出示波器时钟信号，相位可以相对于恢复的时钟信号的相位变化;以及偏移电路，输出电压偏移。 基于电压偏移和示波器时钟信号，比较器输出可用于确定与均衡前后的模拟信号相对应的眼图的数字值。 然后眼图可以与与接收的数据相关联的错误率相关联。

公开(公告)号：US09049020B2

公开(公告)日：2015-06-02

申请号：US12792279

申请日：2010-06-02

申请人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： G06F1/04 ,  H04L1/24

CPC分类号： H04L1/243

摘要： Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.

摘要翻译： 描述了用于简化串行接口测试的电路。 具体地，本发明的一些实施例便于测试接收机的时钟和数据恢复功能。 串行接口可以包括乘法锁相环（MPLL）时钟发生器，发射器和接收器。 MPLL时钟发​​生器可以产生第一时钟信号和第二时钟信号，并且可以改变第一时钟信号和第二时钟信号之间的相位和/或频率差。 在测试期间，发射机和接收机可以彼此直接或电容耦合。 具体来说，在测试期间，串行接口可被配置为使发射机使用第一时钟信号发射数据，并且接收机使用第二时钟信号接收数据。 接收机的时钟和数据恢复功能可以通过比较发送的数据与接收到的数据进行测试。

公开(公告)号：US08125245B2

公开(公告)日：2012-02-28

申请号：US12819650

申请日：2010-06-21

申请人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

发明人： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC分类号： H03K19/094

CPC分类号： H04L25/0278 ,  H03F1/56 ,  H03F2200/387 ,  H04L25/028

摘要： Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.

摘要翻译： 本发明的一些实施例提供一种电压模式发射机。 发射机可以包括配置电路，偏置电路和一组驱动器片。 每个驱动器片可以包括驱动输出值的驱动器晶体管。 每个驱动器片的输出可以与发射器的输出直接或电容耦合。 每个驱动器片还可以包括串联耦合到至少一些驱动晶体管的一个或多个阻抗匹配晶体管。 配置电路可以配置驱动器片段的子集，使得发射机的向下（或向上）阻抗在期望阻抗值的第一公差内。 偏置电路可以偏置驱动器片段子集中的每个驱动器片中的一个或多个阻抗匹配晶体管，使得上（或下））阻抗在下（或向上）阻抗的第二容限内。