摘要:
Systems and methods for preparing inorganic-organic interfaces using organo-transition metal complexes and self-assembled monolayers as organic surfaces. In one embodiment, a silicon wafer is cleaned and reacted with stabilized pirhana etch to provide an oxide surface. The surface is reacted with the trichlorosilyl end of alkyltrichlorosilanes to prepare self assembling monomers (SAMs). The alkyltrichlorosilanes have the general formula R1-R—SiCl3, where R1 is —OH, —NH2, —COOH, —SH, COOCH3, —CN, and R is a conjugated hydrocarbon, such as (CH2)n where n is in the range of 3 to 18. The functionalized end of the SAM can optionally modified chemically as appropriate, and is then reacted with metal-bearing species such as tetrakis(dimethylamido)titanium, Ti[N(CH3)2]4, (TDMAT) to provide a titanium nitride layer.
摘要:
Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.
摘要:
Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.