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    Processor cycle tracking in a controller for two-way set associative cache
    8.
    发明授权
    Processor cycle tracking in a controller for two-way set associative cache 失效
    用于双向组关联缓存的控制器中的处理器周期跟踪

    公开(公告)号：US5392417A

    公开(公告)日：1995-02-21

    申请号：US205129

    申请日：1994-03-01

    申请人： Sundaravarathan R. Iyengar ,  James Nadir

    发明人： Sundaravarathan R. Iyengar ,  James Nadir

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0879

    摘要： A processor communicates over a memory bus with a main memory and a cache by asserting an address strobe signal (ADS) to initiate a memory access. The cache includes a cache controller and a tag random access memory (tag RAM). Internal cycles are tracked by a first logic in the tag RAM that responds to an external cycle (EXCYC) signal and asserts an internal cycle (INCYC) signal during a time when a request to the tag RAM is pending. A second logic combines the INCYC signal with the. ADS to generate an address strobe wait (ADSWAIT) signal. A third logic combines the ADSWAIT signal with the ADS to generate an address strobe cycle (ADSCYC) signal. A fourth logic responsive to one of several end-of-cycle signals generates a terminate signal to signify an end of a current cycle. A fifth logic asserts the EXCYC signal in response to the ADSCYC signal and unasserts the EXCYC signal in response to the terminate signal.

    摘要翻译： 处理器通过断言地址选通信号（ADS）来通过存储器总线与主存储器和高速缓存通信，以启动存储器访问。 高速缓存包括高速缓存控制器和标签随机存取存储器（标签RAM）。 内部周期由标签RAM中的第一个逻辑跟踪，响应外部周期（EXCYC）信号，并在对标签RAM的请求待处理的时间内断言内部周期（INCYC）信号。 第二个逻辑结合了INCYC信号。 ADS生成地址选通等待（ADSWAIT）信号。 第三个逻辑将ADSWAIT信号与ADS相结合，产生地址选通周期（ADSCYC）信号。 响应于几个周期结束信号之一的第四逻辑产生终止信号以表示当前周期的结束。 第五个逻辑响应于ADSCYC信号来断言EXCYC信号，并响应于终止信号而取消发送EXCYC信号。

    Apparatus and method for updating LRU pointer in a controller for two-way set associative cache
    9.
    发明授权
    Apparatus and method for updating LRU pointer in a controller for two-way set associative cache 失效
    用于更新用于双向组关联高速缓存的控制器中的LRU指针的装置和方法

    公开(公告)号：US5530833A

    公开(公告)日：1996-06-25

    申请号：US486132

    申请日：1995-06-06

    申请人： Sundaravarathan R. Iyengar ,  James Nadir

    发明人： Sundaravarathan R. Iyengar ,  James Nadir

    IPC分类号： G06F12/12

    CPC分类号： G06F12/128 ,  G06F12/123

    摘要： A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. There are two lines selected during a line fill to one of the ways. A least recently used (LRU) pointer selects which way to fill on a line fill cycle. The right way is selected for a line fill in response to right hit signal provided that the LRU pointer points to the right way. The LRU pointer is flipped to point to the left way upon the filling of the right line of the right way. The left way is selected for a line fill in response to a left hit signal provided that the LRU pointer points to the left way. The LRU pointer is flipped to point to the right way upon the filling of the left line of the left way.

    摘要翻译： 高速缓存控制器标签随机存取存储器（RAM）被配置成两种方式，每种方式包括标签和有效位存储，用于将目录用于高速缓存数据阵列地址。 两种方式，一种正确的方式和一种左路，每个商店的标签地址。 在行填充中选择了两条线之一。 最近最少使用（LRU）指针选择填充线填充周期的方式。 如果LRU指针指向正确的方式，则选择正确的方法来响应右击信号的行填充。 LRU指针被翻转以指向正确方式的右边线的左边方向。 如果LRU指针指向左侧方向，则左侧方向被选择用于响应于左击信号的行填充。 LRU指针被翻转以指向左侧左侧的左侧填充的正确方式。

    Tag initialization in a controller for two-way set associative cache
    10.
    发明授权
    Tag initialization in a controller for two-way set associative cache 失效
    控制器中的标签初始化用于双向组关联缓存

    公开(公告)号：US5367659A

    公开(公告)日：1994-11-22

    申请号：US216082

    申请日：1994-03-21

    申请人： Sundaravarathan R. Iyengar ,  James Nadir

    发明人： Sundaravarathan R. Iyengar ,  James Nadir

    IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/00 ,  G06F12/04 ,  G06F12/06

    CPC分类号： G06F12/0891 ,  G06F12/123

    摘要： A cache controller tag ram is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. First means are provided for asserting a flush signal upon the condition that a warm start reset is recognized or a power up condition is recognized. Logic causes all pending write requests to be withdrawn in response to the flush signal. The directory is cleared by setting all valid, write protect and least recently used (LRU) bits to zero in both of the ways. Subsequent write requests use a line fill algorithm to ensure that correct data is written into the directory by choosing which way to select for a line fill after the bits have been cleared.

    摘要翻译： 高速缓存控制器标签ram被配置成两种方式，每种方式包括标签和有效位存储，用于在目录中搜索缓存数据阵列地址。 两种方式，一种正确的方式和一种左路，每个商店的标签地址。 第一装置被提供用于在识别到暖启动复位或识别上电状态的条件下断言冲洗信号。 逻辑会导致所有等待写入请求被撤销以响应刷新信号。 通过将所有有效，写保护和最近使用（LRU）位都设置为零，可以清除目录。 随后的写请求使用行填充算法，以确保通过选择在清除位之后为行填充选择哪种方式将正确的数据写入目录。