公开(公告)号：US08698593B2

公开(公告)日：2014-04-15

申请号：US13441596

申请日：2012-04-06

申请人： Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Jang Seok Yun ,  Jin Man Han ,  Sung Jun Kim

发明人： Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Jang Seok Yun ,  Jin Man Han ,  Sung Jun Kim

IPC分类号： H01C1/012

CPC分类号： H01C7/18 ,  H01C17/065 ,  H01C17/06526

摘要： There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).

摘要翻译： 提供了包括陶瓷基板的芯片电阻器; 形成在所述陶瓷基板上并且包括第一导电金属和第一玻璃的第一电阻层; 以及形成在第一电阻层上的第二电阻层，包括第二导电金属和第二玻璃，并且具有比第一电阻层更少的玻璃含量，从而获得相对低的电阻和相对较小的电阻温度系数（TCR ）。

公开(公告)号：US20130154790A1

公开(公告)日：2013-06-20

申请号：US13441596

申请日：2012-04-06

申请人： Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Jang Seok Yun ,  Jin Man Han ,  Sung Jun Kim

发明人： Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Jang Seok Yun ,  Jin Man Han ,  Sung Jun Kim

IPC分类号： H01C1/012 ,  H01C17/00

CPC分类号： H01C7/18 ,  H01C17/065 ,  H01C17/06526

摘要： There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).

摘要翻译： 提供了包括陶瓷基板的芯片电阻器; 形成在所述陶瓷基板上并且包括第一导电金属和第一玻璃的第一电阻层; 以及形成在第一电阻层上的第二电阻层，包括第二导电金属和第二玻璃，并且具有比第一电阻层更小的玻璃含量，从而获得相对低的电阻和相对较小的电阻温度系数（TCR ）。

公开(公告)号：US08179226B2

公开(公告)日：2012-05-15

申请号：US12627111

申请日：2009-11-30

申请人： Heung Bok Ryu ,  Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Yun Gab Choi

发明人： Heung Bok Ryu ,  Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Yun Gab Choi

IPC分类号： H01C1/012

CPC分类号： H01C1/14 ,  H01C1/034 ,  H01C17/006 ,  H01C17/02

摘要： The present invention provides an array type chip resistor including: a substrate formed in a rectangular parallelepiped shape; lower electrodes disposed on both sides of a bottom surface of the substrate at equal spaces; side electrodes extended from some of lower electrodes, formed on outermost edges of both sides of the substrate, in all lower electrodes, to a side surface of the substrate; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes. The array type chip resistor can prevent the resistive element from being damaged due to external impact when mounted since the resistive element is printed inside of the lower electrodes of the bottom surface of the substrate.

摘要翻译： 本发明提供一种阵列式芯片电阻器，包括：形成为长方体形状的基板; 下部电极以等间隔设置在基板的底表面的两侧; 在基板的两侧的最外边缘上形成的一些下部电极在所有下部电极中延伸到基板的侧面的侧面电极; 插入在所述基板的底表面的下电极之间的电阻元件; 覆盖在所述电阻元件上的保护层，所述保护层具有覆盖所述下部电极的一部分和所述电阻元件的两侧; 调平电极与暴露于保护层外侧的下电极接触; 以及形成在平整电极上的镀层。 阵列型芯片电阻可以防止电阻元件在安装时由于外部冲击而被损坏，因为电阻元件被印刷在基板的底表面的下电极内部。

公开(公告)号：US08284016B2

公开(公告)日：2012-10-09

申请号：US12627577

申请日：2009-11-30

申请人： Heung Bok Ryu ,  Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Yun Gab Choi

发明人： Heung Bok Ryu ,  Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Yun Gab Choi

IPC分类号： H01C1/012

CPC分类号： H01C1/14 ,  H01C1/034 ,  H01C17/006 ,  H01C17/02

摘要： The present invention provides an array type chip resistor including: a substrate having a plurality of grooves formed on both sides thereof at equal spaces; lower electrodes formed on both sides of a bottom surface of the substrate; upper electrodes formed on both sides of a top surface of the substrate; side electrodes electrically connected to the upper and lower electrodes; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes. The array type chip resistor can prevent the resistive element from being damaged due to external impact when mounted since the resistive element is printed inside of the lower electrodes of the bottom surface of the substrate.

摘要翻译： 本发明提供了一种阵列型片式电阻器，包括：具有以相等间隔在其两侧形成的多个槽的衬底; 形成在基板的底面两侧的下电极; 上部电极形成在基板的顶表面的两侧; 电连接到上电极和下电极的侧电极; 插入在所述基板的底表面的下电极之间的电阻元件; 覆盖在所述电阻元件上的保护层，所述保护层具有覆盖所述下部电极的一部分和所述电阻元件的两侧; 调平电极与暴露于保护层外侧的下电极接触; 以及形成在平整电极上的镀层。 阵列型芯片电阻可以防止电阻元件在安装时由于外部冲击而被损坏，因为电阻元件被印刷在基板的底表面的下电极内部。

公开(公告)号：US20110057765A1

公开(公告)日：2011-03-10

申请号：US12627577

申请日：2009-11-30

申请人： Heung Bok Ryu ,  Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Yun Gab Choi

发明人： Heung Bok Ryu ,  Jang Ho Park ,  Young Key Kim ,  Ki Won Suh ,  Yun Gab Choi

IPC分类号： H01C1/02

CPC分类号： H01C1/14 ,  H01C1/034 ,  H01C17/006 ,  H01C17/02

摘要： The present invention provides an array type chip resistor including: a substrate having a plurality of grooves formed on both sides thereof at equal spaces; lower electrodes formed on both sides of a bottom surface of the substrate; upper electrodes formed on both sides of a top surface of the substrate; side electrodes electrically connected to the upper and lower electrodes; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes. The array type chip resistor can prevent the resistive element from being damaged due to external impact when mounted since the resistive element is printed inside of the lower electrodes of the bottom surface of the substrate.

摘要翻译： 本发明提供了一种阵列型片式电阻器，包括：具有以相等间隔在其两侧形成的多个槽的衬底; 形成在基板的底面两侧的下电极; 上部电极形成在基板的顶表面的两侧; 电连接到上电极和下电极的侧电极; 插入在所述基板的底表面的下电极之间的电阻元件; 覆盖在所述电阻元件上的保护层，所述保护层具有覆盖所述下部电极的一部分和所述电阻元件的两侧; 调平电极与暴露于保护层外侧的下电极接触; 以及形成在平整电极上的镀层。 阵列型芯片电阻可以防止电阻元件在安装时由于外部冲击而被损坏，因为电阻元件被印刷在基板的底表面的下电极内部。