公开(公告)号：US20170323901A1

公开(公告)日：2017-11-09

申请号：US15661718

申请日：2017-07-27

申请人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

发明人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20160225714A1

公开(公告)日：2016-08-04

申请号：US14974567

申请日：2015-12-18

申请人： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

发明人： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC分类号： H01L23/528 ,  H01L27/115 ,  H01L23/522

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

摘要翻译： 半导体器件可以包括延伸到台阶区域的单元阵列区域中的单元栅极导电图案，延伸穿过单元栅极导电图案的单元阵列区域中的单元垂直结构，单元栅极导电上的单元栅极接触结构 在步进区域中的图案，单元栅极导电图案中的单元栅极接触区域并与单元栅极接触结构对准，与单元栅极导电图案间隔开的第一外围接触结构，与第一外部接触结构间隔开的第二外部接触结构 周边接触结构，第一周边接触结构下面的第一周边接触区域和第二周边接触结构下面的第二周边接触区域。 单元栅极接触区域可以包括第一元件，并且单元栅极导电图案的其余部分可以基本上不包括第一元件。

公开(公告)号：US20160163732A1

公开(公告)日：2016-06-09

申请号：US14962263

申请日：2015-12-08

申请人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

发明人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

摘要翻译： 提供了制造半导体器件的半导体器件和方法。 半导体器件可以包括在半导体衬底上包括开口的半导体图案。 外围晶体管和外围互连结构可以设置在半导体衬底和半导体图案之间。 外围互连结构可以电连接到外围晶体管。 单元栅极导电图案可以设置在半导体图案上。 单元垂直结构可以延伸穿过单元栅极导电图案并且可以连接到半导体图案。 单元位线接触插头可以设置在单元垂直结构上。 位线可以设置在单元位线接触插头上。 外围位线接触结构可以设置在位线和外围互连结构之间。 外围位线接触结构可延伸穿过半导体的开口。

公开(公告)号：US20130187233A1

公开(公告)日：2013-07-25

申请号：US13584193

申请日：2012-08-13

申请人： Jaesun YUN ,  Jeongseok NAM ,  Jinhyun SHIN

发明人： Jaesun YUN ,  Jeongseok NAM ,  Jinhyun SHIN

IPC分类号： H01L27/105

CPC分类号： H01L27/11524 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device may include: a well impurity layer including a cell array region and a well drive region adjacent to the cell array region, the well impurity layer having a first conductivity type; at least one word line on the well impurity layer; at least one bit line crossing the at least one word line on the well impurity layer of the cell array region, the at least one bit line connected to a drain region in the well impurity layer, and the drain region having a second conductivity type; and a well drive line crossing the at least one word line on the well impurity layer of the well drive region, the well drive line connected to the well impurity layer of the first conductivity type.

摘要翻译： 半导体存储器件可以包括：阱杂质层，其包括与电池阵列区域相邻的电池阵列区域和阱驱动区域，阱杂质层具有第一导电类型; 井杂质层上至少有一条字线; 与单元阵列区的阱杂质层上的至少一个字线交叉的至少一个位线，连接到阱杂质层中的漏极区的至少一个位线，以及具有第二导电类型的漏极区; 以及与阱驱动区域的阱杂质层上的至少一条字线交叉的阱驱动线，阱驱动线连接到第一导电类型的阱杂质层。