公开(公告)号：US10043816B2

公开(公告)日：2018-08-07

申请号：US14474867

申请日：2014-09-02

申请人： Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

发明人： Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11582 ,  H01L29/792

摘要： A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

公开(公告)号：US20140061757A1

公开(公告)日：2014-03-06

申请号：US13971279

申请日：2013-08-20

申请人： SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

发明人： SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

IPC分类号： H01L29/788 ,  H01L29/66

CPC分类号： H01L29/788 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

摘要： A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

摘要翻译： 半导体器件包括具有由沟槽限定的多个有源区的半导体衬底。 栅电极与多个有源区交叉。 多个电荷存储单元设置在栅电极和多个有源区域中的每一个之间。 多孔绝缘层设置在栅电极和多个电荷存储单元之间。 多孔绝缘层包括在沟槽上延伸的部分。 空隙设置在多孔绝缘层的延伸部分和沟槽的底表面之间。

公开(公告)号：US20130334593A1

公开(公告)日：2013-12-19

申请号：US13972533

申请日：2013-08-21

申请人： Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

发明人： Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

IPC分类号： H01L29/792

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20130248983A1

公开(公告)日：2013-09-26

申请号：US13898032

申请日：2013-05-20

申请人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.

摘要翻译： 一种三维半导体存储器件包括字形线和栅极层间绝缘层，其交替地层叠在半导体衬底上，同时在水平方向上延伸，垂直沟道层面向字线并从半导体衬底向上延伸，并且沟道 衬垫，其从垂直沟道层延伸并且设置在栅极层间绝缘层的最上层的栅极层间绝缘层上。

公开(公告)号：US20130171806A1

公开(公告)日：2013-07-04

申请号：US13779334

申请日：2013-02-27

申请人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

发明人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

IPC分类号： H01L21/02

CPC分类号： H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

摘要翻译： 提供一种三维半导体存储器件。 三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。 多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。 每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

公开(公告)号：US08445954B2

公开(公告)日：2013-05-21

申请号：US12592404

申请日：2009-11-24

申请人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.

公开(公告)号：US08406062B2

公开(公告)日：2013-03-26

申请号：US12917072

申请日：2010-11-01

申请人： Kwnag Soo Seol ,  Jungdal Choi ,  Sunghoi Hur

发明人： Kwnag Soo Seol ,  Jungdal Choi ,  Sunghoi Hur

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/30

摘要： A memory system, including a nonvolatile memory device, a charge recycler configured to discharge charges from the nonvolatile memory device and recycle the discharged charges, and a controller configured to control the nonvolatile memory device and the charge recycler, wherein the controller controls the charge recycler to recycle the discharged charges, wherein during the recycling the charge recycler charges the charges discharged from the nonvolatile memory device.

摘要翻译： 一种存储器系统，包括非易失性存储器件，电荷回收器，被配置为从非易失性存储器件放电电荷并再循环放电的电荷;以及控制器，被配置为控制非易失性存储器件和电荷回收器，其中控制器控制电荷回收器 以再循环排出的电荷，其中在再循环期间，电荷回收器对从非易失性存储器件排出的电荷进行充电。

公开(公告)号：US08278170B2

公开(公告)日：2012-10-02

申请号：US13165576

申请日：2011-06-21

申请人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

发明人： Changhyun Lee ,  Sunil Shim ,  Jaehoon Jang ,  Sunghoi Hur ,  Hansoo Kim ,  Kihyun Kim

IPC分类号： H01L21/336

CPC分类号： G11C16/28 ,  G11C16/14 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

摘要翻译： 形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。 这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串 系列。

公开(公告)号：US20110169068A1

公开(公告)日：2011-07-14

申请号：US12986553

申请日：2011-01-07

申请人： JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

发明人： JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

摘要翻译： 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US20160351582A1

公开(公告)日：2016-12-01

申请号：US15165135

申请日：2016-05-26

申请人： Nambin Kim ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  CHANGSUB LEE ,  SEUNGHYUN LIM ,  SUNGHOI HUR

发明人： Nambin Kim ,  DAEWOONG KANG ,  DAE SIN KIM ,  KWANG SOO SEOL ,  HOMIN SON ,  CHANGSUB LEE ,  SEUNGHYUN LIM ,  SUNGHOI HUR

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157

摘要： Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

摘要翻译： 本发明提供一种半导体器件，包括基板，垂直堆叠在基板上的栅电极，栅电极之间的绝缘图案，设置成穿过栅电极的活性柱和绝缘图案，并与基板电耦合，以及存储图案， 栅电极和有源支柱以及绝缘图案和有源支柱之间。 栅电极包括在存储器图案和绝缘图案之间延伸的边缘部分。