SEMICONDUCTOR DEVICES
    1.
    发明申请

    公开(公告)号:US20180337193A1

    公开(公告)日:2018-11-22

    申请号:US16047712

    申请日:2018-07-27

    摘要: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20160163730A1

    公开(公告)日:2016-06-09

    申请号:US14959209

    申请日:2015-12-04

    IPC分类号: H01L27/115 H01L29/423

    摘要: A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.

    摘要翻译: 半导体器件包括逻辑结构,该逻辑结构包括布置在电路区域中的逻辑电路和覆盖逻辑电路的下绝缘体,逻辑结构上的存储器结构,插入逻辑结构和电路区域中的存储器结构之间的应力松弛结构 以及连接结构,其沿着沿着电路区域旁边的器件的连接区域延伸的导电路径将存储器结构与逻辑电路电连接。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号:US20160163635A1

    公开(公告)日:2016-06-09

    申请号:US14957113

    申请日:2015-12-02

    摘要: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.

    摘要翻译: 半导体器件包括设置在半导体衬底上的单元半导体图案。 在半导体衬底上设置半导体虚设图案。 半导体虚拟图案与单元半导体图案共面。 第一电路设置在半导体衬底和单元半导体图案之间。 第一互连结构设置在半导体衬底和单元半导体图案之间。 第一虚拟结构设置在半导体衬底和单元半导体图案之间。 第一虚拟结构的一部分与第一互连结构的一部分共面。 与半导体图案不重叠的第二虚拟结构设置在半导体衬底上。 第二虚拟结构的一部分与第一互连结构的一部分共面。 在电池半导体图案和半导体衬底之间以及第一电路和第一互连结构之上设置导电屏蔽图案。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20130009213A1

    公开(公告)日:2013-01-10

    申请号:US13617044

    申请日:2012-09-14

    IPC分类号: H01L27/10

    摘要: Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a pattern on a substrate. The semiconductor devices may also include a capping dielectric layer on the pattern. The semiconductor devices may further include a first nitride layer on the capping dielectric layer. Moreover, the semiconductor devices may include a second nitride layer on the first nitride layer. A concentration of nitrogen in the first nitride layer may be greater than that in the second nitride layer.

    摘要翻译: 提供半导体器件和制造半导体器件的方法。 半导体器件可以在衬底上包括图案。 半导体器件还可以在图案上包括覆盖电介质层。 半导体器件还可以包括在覆盖电介质层上的第一氮化物层。 此外,半导体器件可以包括在第一氮化物层上的第二氮化物层。 第一氮化物层中的氮浓度可以大于第二氮化物层中的浓度。

    SEMICONDUCTOR DEVICES
    8.
    发明申请

    公开(公告)号:US20170330894A1

    公开(公告)日:2017-11-16

    申请号:US15662714

    申请日:2017-07-28

    摘要: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor