公开(公告)号：US20170323901A1

公开(公告)日：2017-11-09

申请号：US15661718

申请日：2017-07-27

申请人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

发明人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20160225714A1

公开(公告)日：2016-08-04

申请号：US14974567

申请日：2015-12-18

申请人： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

发明人： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC分类号： H01L23/528 ,  H01L27/115 ,  H01L23/522

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

摘要翻译： 半导体器件可以包括延伸到台阶区域的单元阵列区域中的单元栅极导电图案，延伸穿过单元栅极导电图案的单元阵列区域中的单元垂直结构，单元栅极导电上的单元栅极接触结构 在步进区域中的图案，单元栅极导电图案中的单元栅极接触区域并与单元栅极接触结构对准，与单元栅极导电图案间隔开的第一外围接触结构，与第一外部接触结构间隔开的第二外部接触结构 周边接触结构，第一周边接触结构下面的第一周边接触区域和第二周边接触结构下面的第二周边接触区域。 单元栅极接触区域可以包括第一元件，并且单元栅极导电图案的其余部分可以基本上不包括第一元件。

公开(公告)号：US20130334593A1

公开(公告)日：2013-12-19

申请号：US13972533

申请日：2013-08-21

申请人： Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

发明人： Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

IPC分类号： H01L29/792

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20160148947A1

公开(公告)日：2016-05-26

申请号：US14845541

申请日：2015-09-04

申请人： Jun-Ho SEO ,  Daewoong KANG ,  Hyoje BANG ,  Changsub LEE ,  Sunghoi HUR

发明人： Jun-Ho SEO ,  Daewoong KANG ,  Hyoje BANG ,  Changsub LEE ,  Sunghoi HUR

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11565

摘要： A memory device includes a stack including gate electrodes vertically stacked on a substrate and having a vertical hole, an active pillar disposed in the vertical hole and providing a vertical channel, a charge storage section interposed between the active pillar and the gate electrodes, a blocking dielectric interposed between the charge storage section and the gate electrodes, a tunnel dielectric interposed between the charge storage section and the active pillar, insulation filling an inner hole of the active pillar, and a fixed charge layer interposed between the filling insulation and the active pillar. Measures are taken to address phenomena in which current would otherwise be adversely affected near an interface between the vertical channel and the filling insulation.

摘要翻译： 存储器件包括：堆叠，其包括垂直堆叠在基板上并具有垂直孔的栅电极，设置在垂直孔中的主动柱并提供垂直沟道;夹在有源柱和栅电极之间的电荷存储部， 介于电荷存储部和栅电极之间的电介质，介于电荷存储部和有源支柱之间的隧道电介质，填充有源支柱的内孔的绝缘填充物和插入填充绝缘体和有源支柱之间的固定电荷层 。 采取措施来解决在垂直通道和填充绝缘体之间的界面附近电流将受到不利影响的现象。

公开(公告)号：US20140029344A1

公开(公告)日：2014-01-30

申请号：US14043256

申请日：2013-10-01

申请人： Changhyun LEE ,  Jinman HAN ,  Doogon KIM ,  Sunghoi HUR ,  Jongin YUN

发明人： Changhyun LEE ,  Jinman HAN ,  Doogon KIM ,  Sunghoi HUR ,  Jongin YUN

IPC分类号： G11C16/10

CPC分类号： G11C16/107 ,  G11C16/0483 ,  G11C16/10 ,  G11C2213/71 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.

摘要翻译： 提供了一种非易失性存储器件的编程方法。 非易失性存储器件包括基板和沿垂直于基板的方向堆叠的多个存储单元。 编程方法将第一电压施加到连接到包括要编程的多个存储器单元的存储单元的同一列中的至少两个存储器串的选定位线，将第二电压施加到连接至少两个的未选定位线 包含要被编程禁止的多个存储单元的存储单元的同一列中的存储器串向同一行中连接到至少两个存储器串的所选择的串选择线施加第三电压，将第四电压施加到未选择的串 选择线连接到同一行中的至少两个存储器串，并且将编程操作电压施加到多个字线，每个字线连接到存储器串中的每个对应的存储单元，其中第一至第三电压是正电压。

公开(公告)号：US20150340376A1

公开(公告)日：2015-11-26

申请号：US14620770

申请日：2015-02-12

申请人： Jintaek PARK ,  Sunghoi HUR ,  Jang-Hyun YOU

发明人： Jintaek PARK ,  Sunghoi HUR ,  Jang-Hyun YOU

IPC分类号： H01L27/115 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.

摘要翻译： 根据示例性实施例，包括具有单元和连接区域的衬底，堆叠在单元区域上的栅电极，垂直沟道结构，焊盘，虚拟柱以及第一和第二半导体图案的三维半导体器件。 垂直沟道结构穿透最下面的栅电极上的栅极，并且包括第一栅极电介质图案。 焊盘从栅电极延伸并且堆叠在连接区域上。 虚拟柱穿透最低垫上的一些焊盘并且包括第二栅极电介质图案。 第一半导体图案在垂直沟道结构和衬底之间。 第二半导体图案位于虚拟柱和衬底之间。 第一和第二栅极电介质图案可以分别在第一和第二半导体图案上。 第二栅极电介质图案可以覆盖第二半导体图案的整个顶表面。

公开(公告)号：US20110073930A1

公开(公告)日：2011-03-31

申请号：US12884668

申请日：2010-09-17

申请人： Yong-Lack CHOI ,  Sunghoi HUR ,  Jaeduk LEE ,  Jungdal CHOI

发明人： Yong-Lack CHOI ,  Sunghoi HUR ,  Jaeduk LEE ,  Jungdal CHOI

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336

摘要： Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.

摘要翻译： 半导体器件及其形成方法。 半导体器件包括在衬底上的隧道绝缘层，隧道绝缘层上的浮动栅极，浮置栅极上的栅极绝缘层，浮动栅极的顶部和第二栅极之间的低介电常数（低k）区域 栅极绝缘层，具有比氧化硅更低的介电常数的低k区域以及栅极绝缘层上的控制栅极。