公开(公告)号：US06681321B1

公开(公告)日：2004-01-20

申请号：US09552856

申请日：2000-04-20

申请人： Jason N. Dale ,  Jim A. Kahle ,  Douglas R. Logan ,  Alex E. Mericas ,  William J. Starke ,  Philip L. Vitale

发明人： Jason N. Dale ,  Jim A. Kahle ,  Douglas R. Logan ,  Alex E. Mericas ,  William J. Starke ,  Philip L. Vitale

IPC分类号： G06F1100

CPC分类号： G06F11/3636

摘要： A method, system and apparatus for instruction execution tracing with out of order speculative processors. Information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions sequenced and executed by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during execution of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions sequenced and executed is known from the sequenced instructions information and the executed instructions information stored in the trace storage device. Hence the instruction execution stream may be reconstructed from the information stored in the trace storage device.

摘要翻译： 用于无序推测处理器的指令执行跟踪的方法，系统和装置。 与指令高速缓存和数据高速缓存的状态相对应的信息与跟随由处理器排序并执行的指令对应的信息一起存储在跟踪存储设备中。 当需要缓存加载时，更新的缓存信息被存储在跟踪存储设备中。 因此，可以从存储在跟踪存储装置中的信息中知道执行指令期间的所有时间的高速缓存的状态。 此外，根据存储在跟踪存储设备中的排序指令信息和执行的指令信息，已知排序并执行的特定指令。 因此，可以从存储在跟踪存储设备中的信息重建指令执行流。

公开(公告)号：US20090276185A1

公开(公告)日：2009-11-05

申请号：US12485863

申请日：2009-06-16

申请人： Alex E. Mericas

发明人： Alex E. Mericas

IPC分类号： G06F15/00

CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

摘要： Detecting and recording events in a processor with a performance monitor in the processor that samples events. The performance monitor in the processor receives performance event signals generated by the processor that indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

摘要翻译： 在具有采样事件的处理器中的性能监视器的处理器中检测和记录事件。 处理器中的性能监视器接收由处理器产生的指示处理器的当前完整事件状态的性能事件信号。 在性能监视器中提供有限数量的计数器，用于仅对选定的性能事件信号的子集进行计数。 在性能监视器中提供了一个事件寄存器，其拦截在执行事件信号的子集之前的性能事件信号。 性能事件信号作为单个单元存储在事件寄存器中。 该单元是一整套可用的性能事件信号，指示处理器当前的完整事件状态。

公开(公告)号：US07548832B2

公开(公告)日：2009-06-16

申请号：US11549136

申请日：2006-10-13

申请人： Alex E. Mericas

发明人： Alex E. Mericas

IPC分类号： G06F11/30

CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

摘要： A method for detecting and recording events in a processor. A performance monitor in the processor receives performance event signals generated by the processor that indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

摘要翻译： 一种用于在处理器中检测和记录事件的方法。 处理器中的性能监视器接收由处理器产生的指示处理器的当前完整事件状态的性能事件信号。 在性能监视器中提供有限数量的计数器，用于仅对选定的性能事件信号的子集进行计数。 在性能监视器中提供了一个事件寄存器，其拦截在执行事件信号的子集之前的性能事件信号。 性能事件信号作为单个单元存储在事件寄存器中。 该单元是一整套可用的性能事件信号，指示处理器当前的完整事件状态。

公开(公告)号：US08949579B2

公开(公告)日：2015-02-03

申请号：US12897008

申请日：2010-10-04

申请人： Miles R. Dooley ,  Venkat R. Indukuru ,  Alex E. Mericas ,  Francis P. O'Connell

发明人： Miles R. Dooley ,  Venkat R. Indukuru ,  Alex E. Mericas ,  Francis P. O'Connell

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0897 ,  G06F2212/6024

摘要： A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyzes the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the ineffectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.

摘要翻译： 信息处理系统（IHS）的处理器在指令处理期间响应于需求负载启动L3高速缓存预取操作。 处理器随机选择L3高速缓存预取作为目标预取指令进行跟踪。 处理器发起L1高速缓存目标预取操作，并将所得到的目标预取指令存储在L1高速缓存中。 如果需求负载到达，则处理器分析目标预取指令的有效性并确定预取数据的来源。 如果请求没有到达，则处理器测试以确定特定预取指令是否在高速缓存中超时并且识别预取操作的无效。 处理器随机抽取多个预取操作，并生成预取有效性和其他有用的预取信息的历史记录。 处理器存储预取有效性信息以便能够减少或去除无效的预取操作。

公开(公告)号：US07200522B2

公开(公告)日：2007-04-03

申请号：US11044450

申请日：2005-01-27

申请人： Alex E. Mericas

发明人： Alex E. Mericas

IPC分类号： G06F11/30

CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

摘要： A method, apparatus, and computer program product are disclosed for sampling all performance event signals generated by a processor. A performance monitor is included in the processor. The performance monitor receives performance event signals from the processor. These performance event signals indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

摘要翻译： 公开了一种用于对由处理器产生的所有性能事件信号进行采样的方法，装置和计算机程序产品。 处理器中包含性能监视器。 性能监视器从处理器接收性能事件信号。 这些性能事件信号表示处理器的当前完整事件状态。 在性能监视器中提供有限数量的计数器，用于仅对选定的性能事件信号的子集进行计数。 在性能监视器中提供了一个事件寄存器，其拦截在执行事件信号的子集之前的性能事件信号。 性能事件信号作为单个单元存储在事件寄存器中。 该单元是一整套可用的性能事件信号，指示处理器当前的完整事件状态。

公开(公告)号：US20120084511A1

公开(公告)日：2012-04-05

申请号：US12897008

申请日：2010-10-04

申请人： Miles R. Dooley ,  Venkat R. Indukuru ,  Alex E. Mericas ,  Francis P. O'Connell

发明人： Miles R. Dooley ,  Venkat R. Indukuru ,  Alex E. Mericas ,  Francis P. O'Connell

IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0897 ,  G06F2212/6024

摘要： A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyses the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the infectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.

摘要翻译： 信息处理系统（IHS）的处理器在指令处理期间响应于需求负载启动L3高速缓存预取操作。 处理器随机选择L3高速缓存预取作为目标预取指令进行跟踪。 处理器发起L1高速缓存目标预取操作，并将所得到的目标预取指令存储在L1高速缓存中。 如果需求负载到达，则处理器分析目标预取指令的有效性并确定预取数据的来源。 如果请求没有到达，则处理器测试以确定特定预取指令是否在高速缓存中超时并且识别预取操作的感染性。 处理器随机抽取多个预取操作，并生成预取有效性和其他有用的预取信息的历史记录。 处理器存储预取有效性信息以便能够减少或去除无效的预取操作。

公开(公告)号：US08055473B2

公开(公告)日：2011-11-08

申请号：US12485863

申请日：2009-06-16

申请人： Alex E. Mericas

发明人： Alex E. Mericas

IPC分类号： G06F11/30

CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

摘要： Detecting and recording events in a processor with a performance monitor in the processor that samples events. The performance monitor in the processor receives performance event signals generated by the processor that indicate the current full event state of the processor. A limited number of counters are provided in the performance monitor for counting only a selected subset of the performance event signals. An event register is provided in the performance monitor that intercepts the performance event signals prior to the subset of the performance event signals being counted. The performance event signals are stored together as a single unit in the event register. The unit is a full set of available performance event signals that indicate the current full event state of the processor.

摘要翻译： 在具有采样事件的处理器中的性能监视器的处理器中检测和记录事件。 处理器中的性能监视器接收由处理器产生的指示处理器的当前完整事件状态的性能事件信号。 在性能监视器中提供有限数量的计数器，用于仅对选定的性能事件信号子集进行计数。 在性能监视器中提供了一个事件寄存器，其拦截在执行事件信号的子集之前的性能事件信号。 性能事件信号作为单个单元存储在事件寄存器中。 该单元是一整套可用的性能事件信号，指示处理器当前的完整事件状态。